A CMOS band-gap reference circuit with sub 1 V operation

Banba, H.; Shiga, H.; Umezawa, Akira; Miyaba, T.; Tanzawa, Toru; Atsumi, S.; Sakui, Koji

doi:10.1109/vlsic.1998.688094

Cited by 45 publications

(17 citation statements)

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“…Note the low output voltage (0.65 V) and low minimum operating voltage (0.85 V) in 1 Reported for the standard CMOS process, simulations showed that V dd = 0:85 should be feasibile with a low-V t process option [13]. combination with the moderate area consumption and the low supply current.…”

Section: E Experimental Resultsmentioning

confidence: 99%

“…The low-voltage reference circuits in [7], [11], and [13] use some kind of resistive division of the voltage across a normal diode. The bandgap circuit in [13] was reported to operate on low supply voltages if low-process options were taken into account in the simulations. The fourth row gives typical results for ordinary CMOS bandgap reference circuits (see Fig.…”

Section: E Experimental Resultsmentioning

confidence: 99%

“…2) Using a fraction of the voltages across the diodes instead of the total voltages, by resistive subdivision [7], [13]. By doing so, the bandgap as "seen" by the circuit is also only a fraction of the material bandgap.…”

Section: B Possible Solutions For Lowmentioning

confidence: 99%

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Low-power bandgap references featuring DTMOSTs

Annema

1999

IEEE J. Solid-State Circuits

164

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This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, lowpower IC's that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 W; the die area is 0.063 mm 2 in a standard digital 0.35-m CMOS process. The second bandgap reference circuit aims at highaccuracy operation ( = = =0:3%) without trimming. It consumes approximately 5 W from a 1.8-V supply voltage and occupies 0.06 mm 2 in a standard 0.35-m CMOS process.

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Section: E Experimental Resultsmentioning

confidence: 99%

Section: E Experimental Resultsmentioning

confidence: 99%

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Low-power bandgap references featuring DTMOSTs

Annema

1999

IEEE J. Solid-State Circuits

164

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“…Scaled-bandgap [1] or MOS-based voltage reference circuits can function with sub-1V supplies. However, they require off-chip precision resistors (one resistor for each bias current generated) and/or on-chip circuitry [7] for voltage-to-current conversion and reference current distribution to different parts of the chip.…”

Section: Introductionmentioning

confidence: 99%

“…Neither of these techniques requires an off-chip resistor and the reference currents can be generated locally in different parts of the chip. The fixed-voltage (FV) technique uses constant voltage generators derived from scaled-bandgap voltage reference circuits [1]. The scaled-V TO (SV) technique, where V TO is the device threshold voltage at absolute zero temperature, does not require voltage references.…”

Section: Introductionmentioning

confidence: 99%

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation

Tang¹,

Narendra²,

De³

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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Body Biasing

Kuroda

Sakurai

Leakage in Nanometer CMOS Technologies

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Reverse body biasing has been widely used in commercial memory chips since the mid-1970s, in order to lower the risk of latchup and memory data destruction, due to lack of substrate contacts for high density cell layout. In logic chips, on the other hand, the substrate and wells are typically biased stably to the ground and power potential with sufficient substrate contacts to ensure that no devices become forward biased, raising the risk of latchup due to unexpected operation of random logic circuits. Since the mid-1990s, however, reverse body biasing has been applied in logic chips for a different reason: power reduction.CMOS power dissipation is increasing rapidly by device scaling [1]. Lowering power supply voltage, VDD, is effective in reducing the power dissipation, but at a cost of increase in propagation delay time. In order to recover the circuit speed, transistor threshold voltage, VTH, should be lowered [2,3,4]. This approach, however, raises two problems.The first problem is rapid increase in sub-threshold leakage in low VJH devices. For every 0.1-volt reduction of VV//, sub-threshold leakage current increases by about one decade. Battery life in portable equipment shortens unless this leakage current is reduced in a standby mode. In standby leakage current (EDDQ) testing, it is difficult to sort out defective chips by monitoring the quiescent power supply current, because leakage current caused by a defect cannot be detected under cover of the increased subthreshold leakage current. Since some kinds of defects are difficult to detect by means other than the EDDQ testing [5], defect mixed rate may be increased. Without the IDDQ testing it is more difficult to develop test vectors for high test coverage as integration level improves. It is also

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A CMOS band-gap reference circuit with sub 1 V operation

Cited by 45 publications

References 1 publication

Low-power bandgap references featuring DTMOSTs

Low-power bandgap references featuring DTMOSTs

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation

Body Biasing

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