A CMOS Antiphase Power Amplifier With an MGTR Technique for Mobile Applications

Park, Jonghoon; Lee, Changhyun; Yoo, Jinho; Park, Changkun

doi:10.1109/tmtt.2017.2709304

Cited by 18 publications

(11 citation statements)

References 33 publications

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“…In the above equations, V P-P and V N,CS,DRV are the peak-to-peak voltage of the input voltage and the common-source gate bias of the driver stage, respectively. Given that the PA is operated at a high power level, a large-signal analysis using the g m,LS and g m3,LS of transistors is necessary for the precise cancellation of the IMD3 [16,17]. Meanings of various symbols used are summarized in the nomenclature section.…”

Section: Antiphase Techniquementioning

confidence: 99%

“…From (4) and 5, we can calculate the overall third-order distortion voltage of the PA, v3rd,PA in the middle-power region as follows: However, although the linear region is expanded through the cancellation of the IMD3 between the driver and power stages in the high-power region, the IMD could deteriorate in the middle-power region, as shown in Figure 2 [16,17]. To analyze the IMD3 in the middle-power region, we use the desired voltage, v Sig,DRV and the third-order distortion voltage, v 3rd,DRV , which are generated in the output of the driver stage as follows [17]:…”

Section: Imd3 In the Middle-power Regionmentioning

confidence: 99%

“…To obtain sufficient linearity and thereby resolve large backed-off level issues in CMOS PAs, various techniques, such as capacitance compensation, the multi-gate transistor (MGTR), and antiphase have been introduced [10][11][12][13][14][15][16][17]. The capacitance compensation technique cancels out the capacitance variation of primary transistors using auxiliary transistors that have contrasting capacitance variations [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…The capacitance compensation technique cancels out the capacitance variation of primary transistors using auxiliary transistors that have contrasting capacitance variations [13][14][15]. As one of the meaningful linearization techniques, the antiphase technique could successfully suppress the IMD3s through the cancellation of IMD3s between the driver and power stages [16][17][18][19][20]. In this In this work, we investigate the possibility of CMOS PAs with a p-channel metal oxide semiconductor (PMOS) driver stage to suppress the nonlinearities such as IM, AM-AM, and AM-PM distortions.…”

Section: Introductionmentioning

confidence: 99%

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Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

et al. 2020

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We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s.

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Section: Antiphase Techniquementioning

confidence: 99%

Section: Imd3 In the Middle-power Regionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

et al. 2020

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“…In particular, the IMD3 directly affects the adjacent channel leakage ratio (ACLR) and adjacent channel power ratio (ACPR), which are strictly specified by wireless communication standards. As a result, various techniques to suppress the IMD3 have been researched, such as the anti-phase technique [5,6]. This technique utilizes the cancellation of IMD3s generated by the driver and power stages of the power amplifier.…”

Section: Introductionmentioning

confidence: 99%

Suppression of Imd3 in Cmos Power Amplifier Using Bias Circuit of Common-Gate Transistor With Cascode Structure

Kim¹,

Lee²,

Yoo³

et al. 2019

PIER M

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In this study, we propose a technique to improve the linearity of complementary metaloxide semiconductor (CMOS) power amplifiers with a cascode structure. From the investigation of the influence of the impedance of an envelope signal on the linearity, we find that the load impedance of the envelope signal of the common-source transistor should be reduced. To obtain alow load impedance of the envelope signal, we reduce the value of the gate resistor of the common-gate transistor. After investigating the influences of the value of the resistance on the third-order intermodulation distortion (IMD3), we extract the optimum value of the resistance. We also consider the electrostatic discharge protection issue and the effects of the variations in the parasitic components of bond-wires, in the process of the extraction of the optimum value. To verify the feasibility of the optimization technique of the resistance of the bias circuit of the common-gate transistor of the amplifier, we design a power amplifier using a 180-nm RFCMOS process for wireless local area network (WLAN) 802.11n applications. We obtain the measured maximum linear output power of 22.2 dBm with a 26.7% power-added efficiency and a 3.72% error vector magnitude. We use an 802.11n modulated signal with 64-QAM (MCS7) at 65 Mb/s. From the measured results, we successfully verify the feasibility of the proposed optimization technique of the resistance of the bias circuit of the common-gate transistor.

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A power amplifier with bandwidth expansion and linearity enhancement in 130 nmcomplementary metal‐oxide‐semiconductorprocess

Cao

Liu

et al. 2021

Int J RF Microw Comput Aided Eng

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A power amplifier with bandwidth expansion and linearity enhancement in 130 nm complementary metal-oxide-semiconductor (CMOS) process is presented. A LC connected dual-resonant network is proposed to achieve good broadband performance and high out-band rejection capability simultaneously. Furthermore, the advanced multiple-gated transistor technique is employed to cancel out odd-order intermodulation and harmonic distortions. The PA is implemented in 130 nm CMOS process with an area of 1.17 mm × 0.92 mm.Measurement results demonstrate that the PA exhibits a peak power gain of 8 dB with a relative bandwidth of 38% while maintaining a low reflection coefficient of −23.2 dB, maximum saturation output power of 15.6 dBm, maximum OP1dB and OIP3 of 14.3 dBm and 19 dBm, and a peak power added efficiency of 21.3%, respectively. In addition, an out-band rejection of 20 dB and 23.2 dB at 6.1 GHz and 14 GHz are measured.

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A CMOS Antiphase Power Amplifier With an MGTR Technique for Mobile Applications

Cited by 18 publications

References 33 publications

Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

Suppression of Imd3 in Cmos Power Amplifier Using Bias Circuit of Common-Gate Transistor With Cascode Structure

A power amplifier with bandwidth expansion and linearity enhancement in 130 nmcomplementary metal‐oxide‐semiconductorprocess

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