A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

Wang, Zheng; Chiang, Pei-Yuan; Nazari, Peyman; Wang, Chuncheng; Chen, Zhiming; Heydari, Payam

doi:10.1109/jssc.2013.2297415

Cited by 231 publications

(82 citation statements)

References 34 publications

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“…Yu et al presented an On-Off Keying (OOK) implementation in the 30-90 GHz range capable of providing up to 48 Gb/s [30], enough for the evaluations carried out in this paper. With technology advances, transceivers providing even larger bandwidths at 100-300 GHz bands are expected [16], [39]. An additional consideration is the bit error rate, for which most WNoC works have assumed to be commensurate to that of a wire (∼ 10 −15 ) [8], [30].…”

Section: Physical Layermentioning

confidence: 99%

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Abadal

Torrellas

Alarcón

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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Abstract-On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.

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Section: Physical Layermentioning

confidence: 99%

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Abadal

Torrellas

Alarcón

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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“…Si-device technologies have started to reveal their potential in these 2-3 years [11], [12], [41], [42]. A power combining technique using integrated array antennas has proven to be effective to increase an output power in Si-CMOS transmitter ICs [43], [44].…”

Section: Transmitters and Receiversmentioning

confidence: 99%

Recent Progress and Future Prospect of Photonics-Enabled Terahertz Communications Research

Nagatsuma

Carpintero

2015

IEICE Trans. Electron.

119

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SUMMARYThis paper reviews a recent progress in terahertz wireless communications enabled by photonics technologies. After briefly summarizing transceiver configurations with electronics and photonics technologies, photonics-based approaches to achieving over 100-Gbit/s data rates are discussed. Then, some of our updated results on real-time wireless transmission experiments using discrete components are shown at data rates up to 50 Gbit/s. Finally, integration technologies are described by demonstrating latest advances in integrated optical sources and transmitters.

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“…CMOS on-chip antennas tend to be significantly lossier than off-chip antennas due to the presence of silicon substrate. However, it is difficult to realize low-loss wired connection to off-chip components at terahertz frequencies, and on-chip antennas are used to solve that problem [26,27].…”

Section: On-chip Power-line Decoupling Planar Circuits and Antennasmentioning

confidence: 99%

“…For example, Wang et al reported a 210-GHz transceiver in 32-nm SOI CMOS [27]. Park et al demonstrated a 260-GHz transceiver in 65-nm CMOS [26].…”

Section: Transceiversmentioning

confidence: 99%

Recent progress and prospects of terahertz CMOS

Fujishima

Amakawa

2015

IEICE Electron. Express

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Recent progress and prospects of terahertz CMOS integrated circuits is reviewed. The development of terahertz CMOS is somewhat different from the conventional digital and RF CMOS evolution, in that it is not fueled as much by technology scaling. Rather, the key enablers are progress in high-frequency device characterization and modeling techniques and also in design techniques near transistor's active operation limit, f max .

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A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

Cited by 231 publications

References 34 publications

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Recent Progress and Future Prospect of Photonics-Enabled Terahertz Communications Research

Recent progress and prospects of terahertz CMOS

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