A Class of Maximum-Period Nonlinear Congruential Generators Derived From the R&amp;eacute;nyi Chaotic Map

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

Zidan

et al. 2013

Abstract-This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Shortterm predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.

“…(1b) where D controls attractor size [3]. The Euler approximation (with step size h = 2 −k ) is applied:…”

Section: A Digital Realizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation

Radwan

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

Zidan

et al. 2013

“…Therefore, a fully digital approach to chaos generators is necessary for applications requiring repeatable oscillators, including cryptography and spread-spectrum communication. However, digital implementations of chaos-based pseudo-random number generators [25][26][27][28][29] have remained reliant on 1-D discrete chaotic maps. This notion is natural given the direct application in the digital do-main but resulting systems have the following drawbacks: a) They are slow and large due to multiplication, b) They have low throughput due to 1-D output and c) They suffer from windows of periodicity that require more complex architectures to overcome.…”

Section: Introductionmentioning

confidence: 99%

“…800-22 test suite [40] to indicate statistical randomness. The resulting PRNGs enjoy high-throughput when compared to other chaosbased designs [25][26][27][28][29] in spite of implementation on a previousgeneration Xilinx Virtex 4 FPGA. All systems are designed in Verilog HDL and experimentally verified with logic utilization less than 1.73% and throughput up to 15.59 Gbits/s for the native chaotic systems and up to 8.77 Gbits/s for the resulting PRNGs.…”

Section: Introductionmentioning

confidence: 99%

Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77Gbits/s

Microelectronics Journal

Zidan

Barakat

et al. 2013

This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100x higher maximum Lyapunov exponent than the original jerkequation based chaotic systems. The resulting chaotic output is shown to pass the NIST sp. 800-22 statistical test suite for pseudorandom number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators.

“…Chaotic oscillators have been emphasized for applications in random number generation [1]- [6] wherein the repeatable, reliable and high-performance chaotic sources required for these applications [7] are difficult to realize using analog circuits with chaos degradation due to established issues of PVT-sensitivity [8]. In particular, multi-scroll chaos generators have been exhaustively studied [9]- [12], wherein the limitations on the dynamic range of analog components and low supply voltages has restricted the number of scrolls that can be realized due to complex circuitry needed for control [13] unless mixed-signal approaches are used [14].…”

Section: Introductionmentioning

confidence: 99%

Fully digital 1-D, 2-D and 3-D multiscroll chaos as hardware pseudo random number generators

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

Radwan

Salama

2012

Abstract-This paper introduces the first fully digital implementation of 1-D, 2-D and 3-D multiscroll chaos using the sawtooth nonlinearity in a 3rd order ODE with the Euler approximation. Systems indicate chaotic behaviour through phase space boundedness and positive Lyapunov exponent. Low-significance bits form a PRNG and pass all tests in the NIST SP. 800-22 suite without post-processing. Real-time control of the number of scrolls allows distinct output streams with 2-D and 3-D multiscroll chaos enabling greater controllability. The proposed PRNGs are experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.25%, throughput up to 5.25 Gbits/s and up to 512 distinct output streams with low cross-correlation.