A Circuit for Reducing Large Transient Current Effects on Processor Power Grids

Hailu, Engidaw Abel; Boerstler, D.; Miki, Koozi; Qi, Jun; Wang, M.; Riley, Merle E.

doi:10.1109/isscc.2006.1696285

Cited by 15 publications

(9 citation statements)

References 1 publication

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“…The dynamically adaptive clock gating removes the clock edges that would otherwise degrade path timing margin. If clock gating occurs for many cycles, clock dithering [12] can prevent new V CC droops when resuming execution. As an alternative to clock gating for multiple cycles, an adaptive response could reduce F CLK in half with a clock-divider circuit.…”

Section: Adaptive Clock Distributionmentioning

confidence: 99%

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

et al. 2013

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Intel h VARIABILITY IN DEVICE and circuit parameters is one of the primary challenges in the semiconductor industry today. Parameter variations adversely affect the performance and energy efficiency of microprocessors across all market segments, ranging from small embedded cores in a system-on-chip (SoC) to large multi-core servers. A distinguishing feature of a parameter variation is the temporal characteristic (i.e., static or dynamic). A static parameter variation results from variability in the manufacturing process. Although manufacturing-induced parameter variations change from die to die, these parameter variations are static per die. A dynamic parameter variation occurs in time during the microprocessor operation as environmental and workload conditions change, which is the focus of this paper. Examples of dynamic parameter variations include supply voltage ðV CC Þ droops, temperature changes, and transistor aging. V CC droops result from abrupt changes in microprocessor switching activity, inducing large current transients in the power delivery system. The magnitude and duration of a V CC droop depend on the interaction of capacitive and inductive parasitics at the board, package, and die levels with changes in current demand [1], [2]. V CC droops primarily affect circuits globally across the die and may occur with frequencies ranging in delay from a few nanoseconds (i.e., high frequency) to a few microseconds (i.e., low frequency). High-frequency V CC droops traditionally result in the largest V CC magnitude change, and thus, the most severe V CC droop [2]. In today's high-performance microprocessors, the high-frequency V CC droop is the dominant dynamic variation source affecting performance and energy efficiency. Temperature variations depend on workload, environmental conditions, and the heat-removal capability of the package. Temperature changes at a relatively slow time scale and generally affects a large portion of the die area. Transistor aging slowly degrades the drive current over time as a function of gate bias and temperature conditions. Higher gate voltages or temperatures accelerate the transistor aging effect. After removing the gate bias, the drive current degradation from aging starts to recover. For this reason, transistor aging and recovery are highly sensitive to the local transistor activity factor and state probability.Conventional microprocessor designs build in clock frequency ðF CLK Þ and/or V CC guardbands to ensure correct functionality while in the presence of worst-case dynamic variations. Consequently, these Editor's notes: This paper focuses on techniques to build more effective circuits for dynamic variation tolerance. Three main approaches are presented based on adaptive circuits, error detection and recovery techniques, and adaptive clock distribution. The tradeoffs in effectiveness and overhead of these different solutions are discussed.

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Section: Adaptive Clock Distributionmentioning

confidence: 99%

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

et al. 2013

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“…3.4. The noise at a particular frequency is estimated by multiplying the impedance with the current component at that frequency [15,41]. A model for 3D ICs, based on distributed models of the on-chip and package power supply structures, is shown in Fig.…”

Section: The Basics Of Power Deliverymentioning

confidence: 99%

Thermal and Power Delivery Challenges in 3D ICs

Jain

Zhou

Kim

et al. 2009

Integrated Circuits and Systems

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Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

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“…Resonant supply noise which resides in the frequency range 40MHz-300MHz [1][2] and is formed between the package inductance and on-chip capacitance, has been identified as the one of the major performance limiting factors of modern low voltage processors ( Fig. 1) [3].…”

Section: Introductionmentioning

confidence: 99%

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

Paul

Amrein

Gupta

et al. 2012

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

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Abstract-In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.

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A Circuit for Reducing Large Transient Current Effects on Processor Power Grids

Cited by 15 publications

References 1 publication

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

Thermal and Power Delivery Challenges in 3D ICs

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

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