A chip-to-chip clock-deskewing circuit for 3-D ICs

Chuang, Ai-Jia; Yu, Liang; Yang, Ching-Yuan

doi:10.1109/iscas.2012.6271574

Cited by 6 publications

(3 citation statements)

References 5 publications

(3 reference statements)

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“…A common approach to address the clock synchronization problem across multiple dies in a 3D stack is to use Delay-Locked Loops (DLLs) to drive the TSVs to help ensure that the local clock networks on each die are synchronized. For example, the authors of [28] have proposed a dual-delaylocked loop (D-DLL) for die-to-die clock deskew applications, allowing for a clock synchronization within 2ps for 550MHz-1.5GHz clock signals. The authors of [27] have proposed an approach based on dual-locking DLL that allows for clock synchronization without the need to replicate TSV delays.…”

Section: Clock Synchronization In a 3d Stackmentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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3D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an FPGA that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a non-programmable die by replacing the defective functionality with functionality on the FPGA. In this article, we discuss what additional logic must be added to an ASIC die to allow such a bypass to occur. We then show through detailed simulation of a 2.5D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies.Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

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Section: Clock Synchronization In a 3d Stackmentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…However, the regularly switching the direction of the forward path and the feedback path and perform fine-tuning in two DLLs may cause a relatively large error during phase maintaining mode. The dual-delay-locked loop (D-DLL) [4] does not need to switch the direction of the forward path and the feedback path since a bidirectional buffer is applied. However, two DLLs are working at the same time which increases the design complexity to maintain the stability of the D-DLL.…”

Section: Figure 5 Layout Of the Test Chipmentioning

confidence: 99%

“…A dual-delay-locked loop (D-DLL) [4] is proposed for die-to-die clock deskew circuit applications. Two analog charge-pump-based DLLs are used in this design.…”

Section: Introductionmentioning

confidence: 99%

All-digital delay-locked loop for 3D-IC die-to-die clock synchronization

Chung

Hou

2014

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test

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In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can tolerate delay variations in TSVs and synchronize the clock signals in multiple layers of a given 3D-IC. Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs. Subsequently, the proposed ADDLL can further compensate for the clock skew of clock signals in multiple layers of a 3D-IC. After ADDLL is locked, the clock skew or phase error is eliminated, and data transfer between dies can be performed synchronously. The proposed design can operate from 300MHz to 1GHz. The proposed ADDLL is implemented in a standard performance 90nm CMOS process, and the area of the ADDLL per die is 0.045mm 2 . The power consumption of the proposed ADDLL is 3.27mW at 1GHz, and the maximum phase error of clock signals in multiple layers of a given 3D-IC is 21.9ps.Index Term all-digital delay-locked loop, through silicon via (TSV), 3D-IC, digitally controlled delay line.

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New Approach of IO Cell Placement Addressing Minimized Data and Clock Skews in Top Level

Arman

2023

2023 IEEE East-West Design &Amp; Test Symposium (EWDTS)

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A chip-to-chip clock-deskewing circuit for 3-D ICs

Cited by 6 publications

References 5 publications

Repairing a 3-D Die-Stack Using Available Programmable Logic

Repairing a 3-D Die-Stack Using Available Programmable Logic

All-digital delay-locked loop for 3D-IC die-to-die clock synchronization

New Approach of IO Cell Placement Addressing Minimized Data and Clock Skews in Top Level

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