A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering

Hasan, Sakib; Majumder, Md. Badruddoja; Shanta, Aysha S.; Uddin, Mesbah; Rose, Garrett S.

doi:10.1007/s41635-019-00085-7

Cited by 11 publications

(7 citation statements)

References 25 publications

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“…AND and NAND are represented by 1(0001) and 14(1110), respectively. As shown in [7], multiple configurations for implementing basic logic gates, enabled by nonlinear dynamics, can lead to obfuscation against power side channel attack. The proposed design can also be leveraged for the same goal.…”

Section: Chaotic Oscillatormentioning

confidence: 99%

“…The nonlinear dynamics inherent in a chaos-based design enables developing complex (e.g. multi-input, multi-output) logic gates using the same circuit [7]. The possible functions for an n-input logic gate is 2 2 n .…”

Section: Enhancement Of the Functionality Spacementioning

confidence: 99%

“…For obfuscation applications, it is highly desirable to have a large functionality space so that multiple reliable configurations can be chosen for implementing a single function. This can be leveraged to ensure the security of chaosbased computing systems against side-channel power analysis based attacks [7], [14]. Previously, this was achieved using many iterations but this poses a problem since the resulting gate becomes increasingly unreliable.…”

Section: Enhancement Of the Functionality Spacementioning

confidence: 99%

“…In order to reduce the hardware cost, researchers have made an effort to come up with simpler transistor-level discrete maps with good chaotic properties [1], [5]. Recently, researchers have been exploring how to leverage the large functionality space provided by these discrete map chaotic circuits for security applications [6], [7]. Most chaotic maps have only one bifurcation parameter where the space is extended by increasing the number of iterations.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Hasan

Shanta

Paul

et al. 2020

2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)

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In this paper, a novel chaotic map is introduced using a voltage controlled negative differential resistance (NDR) circuit composed of an n-channel and a p-channel silicon-on-insulator (SOI) four-gate transistor (G 4 FET). The multiple gates of the G 4 FET are leveraged to create a discrete chaotic map with three bifurcation parameters. The three tunable parameters are the gain of a transimpedance amplifier (TIA), top-gate voltage of nchannel G 4 FET, and top-gate voltage of p-channel G 4 FET. Two methods are proposed for building chaotic oscillators using this discrete map. The effect of altering bifurcation parameters on chaotic operation is illustrated using bifurcation diagrams and Lyapunov exponent. A design methodology for building flexible and reconfigurable logic gate is outlined and the consequent enhancement in functionality space caused by the existence of three independent bifurcation parameters is demonstrated and compared with previous work.

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Section: Chaotic Oscillatormentioning

confidence: 99%

Section: Enhancement Of the Functionality Spacementioning

confidence: 99%

Section: Enhancement Of the Functionality Spacementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Hasan

Shanta

Paul

et al. 2020

2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)

Self Cite

View full text Add to dashboard Cite

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“…The initial state sensitivity is popularly known as the 'butterfly effect', after being coined by Lorenz in a lecture [6], as if a butterfly flapped its wings in Brazil a few weeks earlier and as a result, eventually, that minor perturbation has changed the nice sunny weather in Texas into a tornado. This deterministic aperiodicity and the sensitive dependence on the initial state of chaotic systems have proven their utility in numerous security applications such as data encryption [7], random number generation [8], [9], reconfigurable logic [10], [11], Physically Unclonable Function (PUF) [12], side-channel attack mitigation [13], secure communication [14], logic obfuscation [15] and so on.…”

Section: Introductionmentioning

confidence: 99%

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

et al. 2022

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We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 nm designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and is demonstrated using a novel random number generator (RNG) design. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), this proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise that renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded maps, significantly low area and power overhead are achieved in the RNG design. The cryptographic applicability of the RNG is verified as the generated random sequences pass four standard statistical tests namely, NIST, FIPS, Diehard, and TestU01.

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Reliable and secure memristor-based chaotic communication against eavesdroppers and untrusted foundries

Vishwakarma

Monani

Hedayatipour

et al. 2023

Discov Internet Things

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Chaos is a deterministic phenomenon that occurs in a non-linear dynamic system under specific condition when the trajectories of the state vector become periodic and extremely sensitive to the initial conditions. While traditional resistor-based chaotic communications are primarily concerned with the safe transfer of information across networks, the transceivers themselves can be compromised due to outsource manufacturing. With the growth of wireless sensors in resource-constrained implantable and wearable devices, chaotic communication may be a good fit if the information transmitted is reliable and the transmitter devices are secure. We believe that memristor, as the fourth fundamental two-terminal circuit element, can close the gap between reliable communication and secure manufacturing since its resistance can be programmed and saved by the designer and not the foundry. Thus, in this paper, we propose a memristor-based Chua’s chaotic transceiver that is both reliable in the presence of eavesdroppers and secure against untrusted foundries. Specifically, we consider the pair of transmitter and receiver under the same memristor value to show the possibility of uninterrupted communication as well as cases where different values of memristors are used to find out the possible range in which the message can still be meaningfully decoded. Experimental results confirm that both reliable communication and secure design can be achieved via our proposed memristor-based chaos transceivers.

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A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering

Cited by 11 publications

References 25 publications

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

Reliable and secure memristor-based chaotic communication against eavesdroppers and untrusted foundries

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A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering

Cited by 11 publications

References 25 publications

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

Reliable and secure memristor-based chaotic communication against eavesdroppers and untrusted foundries

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Product

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Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map