A cell library of scalable neural network classifiers for rapid low-power vision and cognition systems design

König, Andreas; Gunther, A.; Döge, Jens; Eberhardt, Michael

doi:10.1109/kes.2000.885811

Cited by 3 publications

(4 citation statements)

References 9 publications

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“…In addition to the ANN area and execution time control, there has been an increasing emphasis on the low‐power ANN implementation [9, 20, 21]. In [9], the authors reported the performance of a distance‐computing unit using redundant arithmetic.…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…The average gain was equal to 11% in delay and 18% in power consumption after a comparison with classical arithmetic. The work of Koeing , et al [21] presented a cell library for a low‐power ANN for vision applications. During the literature review on this topic, it was noticed that most of these approaches utilised general circuit level low‐power techniques.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Implementation of a low‐power LVQ architecture on FPGA

Najoua

Boubaker

Bedoui

2017

IET Circuits, Devices & Syst

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This study presents an architecture-optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low-power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors' architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.

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Section: Introduction and Related Workmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

Implementation of a low‐power LVQ architecture on FPGA

Najoua

Boubaker

Bedoui

2017

IET Circuits, Devices & Syst

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show abstract

“…The increasing demand for computational power of neural networks is leading to achieve low power VLSI circuits [6]. Furthermore, as the ANN is getting more pervasive in mobile embedded devices [7,8], the power requirement of ANN hardware is proving to be a major limitation [9].…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, as the ANN is getting more pervasive in mobile embedded devices [7,8], the power requirement of ANN hardware is proving to be a major limitation [9]. As a result, there has been increasing emphasis on the low-power implementation of the ANN [6,10,11].…”

Section: Introductionmentioning

confidence: 99%

Power scalable implementation of Artificial Neural Networks

Modi

Wilson

Brown

2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

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As the use of Artificial Neural Network(ANN) in mobile embedded devices gets more pervasive, power consumption of ANN hardware is becoming a major limiting factor. Although considerable research efforts are now directed towards low-power implementations of ANN, the issue of dynamic power scalability of the implemented design has been largely overlooked. In this paper, we discuss the motivation and basic principles for implementing power scaling in ANN Hardware. With the help of a simple example, we demonstrate how power scaling can be achieved with dynamic pruning techniques.

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Low-Power Massively Parallel Feature Computation for Application-Specific Integrated Vision Systems

Mayr¹,

König²

2002

Soft Computing and Industry

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A cell library of scalable neural network classifiers for rapid low-power vision and cognition systems design

Cited by 3 publications

References 9 publications

Implementation of a low‐power LVQ architecture on FPGA

Implementation of a low‐power LVQ architecture on FPGA

Power scalable implementation of Artificial Neural Networks

Low-Power Massively Parallel Feature Computation for Application-Specific Integrated Vision Systems

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