Power scalable implementation of Artificial Neural Networks

Abstract

As the use of Artificial Neural Network(ANN) in mobile embedded devices gets more pervasive, power consumption of ANN hardware is becoming a major limiting factor. Although considerable research efforts are now directed towards low-power implementations of ANN, the issue of dynamic power scalability of the implemented design has been largely overlooked. In this paper, we discuss the motivation and basic principles for implementing power scaling in ANN Hardware. With the help of a simple example, we demonstrate how power scaling can be achieved with dynamic pruning techniques.

Implementation of a low‐power LVQ architecture on FPGA

“…By using the two last equations, (3) and ( 4), of the estimated dynamic power models, we succeed in establishing a model (5) for the LVQ's dynamic power in function of the number of slices, delay and topology (number of inputs and output neurons) P dyn slices, delay, topology = a 2 × inputs + b 2 slices +c 2 × output neuron + d 2 delay…”

“…Intensive ANN computing requires a great-power use to solve these problems. Following the reconfigurable system's increase in power consumption, the ANN hardware power consumption becomes a very important implementation issue [3][4][5][6]. Also, the present advances in the semiconductor integration industry thrusts more the development of low-power system on chips (SOCs) [7][8][9].…”