An encapsulated writing style of Verilog is described together with models for a corresponding scheduler and synthesizer. The method provides a middle ground between synthesis f r o m behavioral specijlcations, which implies decisions too dificult for architectural synthesis, and synthesis f r o m pure structural specijkations, which necessitates providing full details of the controller and netlist. The input writing style is designed t o be as concise as possible. This is done by the encapsulation of the functionality of major submodules, and implicit (infered) control. In this way it is possible t o describe complex functional architectures in a n economical and transparent manner. This description can be transformed semi-automatically by steps through intermediate styles and eventually t o a pure structural specification containing full details of timing invocations and interconnections t o appropriate controllers. At each stage after the first, the writing styles can be fully accessible t o native Verilog simulators. The efficiency and economy of this style is demonstrated by a simulation of the well known DLX processor benchmark with full pipeline bypasses.