Sixth Annual IEEE International ASIC Conference and Exhibit
DOI: 10.1109/asic.1993.410750
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A cell-based datapath synthesizer for ASICs

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“…There are some other precedents in the general literature for the approach we will be taking here with Verilog. In particular: That the datapath and control sections should be distinctly treated, eg [4]; That a specification for synthesis should be couched in terms of synthesizable parameterizable modules [13], [9], 1111; That the speci-0-8 186-7082-7/95 $04.00 0 1995 lEEE fication and simulation of the zero-delay functionality should be separated from that incorporating tiiming [lo].…”
Section: Introductionmentioning
confidence: 99%
“…There are some other precedents in the general literature for the approach we will be taking here with Verilog. In particular: That the datapath and control sections should be distinctly treated, eg [4]; That a specification for synthesis should be couched in terms of synthesizable parameterizable modules [13], [9], 1111; That the speci-0-8 186-7082-7/95 $04.00 0 1995 lEEE fication and simulation of the zero-delay functionality should be separated from that incorporating tiiming [lo].…”
Section: Introductionmentioning
confidence: 99%