A CDR with a digital threshold decision technique and a cyclic reference injected DLL frequency multiplier wtih a period error compensation loop

A 2-5 Gbps fully differential 3X oversampling CDR for high-speed serial data link

“…The proposed CDR performance parameters are compared with reported digital CDRs. The CDR has low power consumption than other reported CDR except the CDR reported in [4], which can operate up to 3 Gbps. The acquisition time of the proposed CDR is shorter and satisfies the requirements for the GPON applications.…”

“…• This work is an extension to the work done by Carleton's VLSI group [4]. There are a number of areas in which the CDR in this thesis is significantly different from the previous work.…”

“…narrow bandwidth will result in a longer acquisition time. A longer acquisition time requires an increased number of preamble bits and this increased number of bits will reduce the efficiency of the CDR [4]. Longer acquisition time makes the PLL based CDR unsuitable for burst-mode applications such as gigabit passive optical networks (GPON), which require fast acquisition [30].…”

“…Thus maximum allowable jitter that remains constant (A UI) is referred to as the jitter tolerance at high jitter frequency. Jitter at a frequency lower than f cl can be tracked up to a certain peak-to-peak jitter amplitude, and because of the CDR loop characteristics the amplitude variation can have a slope of 20 dB/decade [4]. The solid curve in Fig.…”

“…A small time step results in a large number of signal points that needs to be evaluated. Therefore the simulation time will be dramatically increased for a simulation such as the one used to find jitter tolerance [4].…”