A case of autoimmune pancreatitis found by the onset of obstructive jaundice

Ono, Chihiro; Yaegashi, Kanji; Ono, Mikiyo

doi:10.11641/pde.64.2_144

Cited by 2 publications

(2 citation statements)

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“…2(c). This differs from a partially depleted SOI DTMOS [6], in which the operation voltage is strictly limited to as low as 0.1 V at 120°C due to a rapid increase in the pn-forward junction current [7]. Fourth, due to the thin silicon, SER [16] and pn-junction current are significantly reduced.…”

Section: Features Of Planar Double-gate Fd-soimentioning

confidence: 99%

Low-voltage limitations of deep-sub-100-nm CMOS LSIs

Itoh

Yamaoka

Kawahara

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Deep-sub-100-nm CMOS LSIs using a bulk CMOS device and a planar double-gate FD-SOI device are compared in terms of the low-voltage limitation of RAM cells, sense amplifiers, and logic gates. The limitation strongly depends on the ever-larger V T variation, especially in SRAM cells and logic gates, and is improved by the FD-SOI. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: High-V DD bulk CMOS LSIs for low-cost low-standby-current applications, and low-V DD FD-SOI LSIs for low-power applications.

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Section: Features Of Planar Double-gate Fd-soimentioning

confidence: 99%

Low-voltage limitations of deep-sub-100-nm CMOS LSIs

Itoh

Yamaoka

Kawahara

2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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“…5(b), which differs from the partially-depleted (PD) SOI DTMOST [14]. Note that the PD-SOI cannot take a positive well voltage higher than around 0.1 V at 120°C to prevent a rapidly increasing pn-forward current [15]. 6-T and 4-T SRAM cells [13,16,17] with dynamic V T circuits are shown in Fig.6.…”

Section: Signal Voltage Of Sram Cellsmentioning

confidence: 99%

Ultra-Low Voltage Nano-Scale Embedded RAMs

Itoh

2006

2006 IEEE North-East Workshop on Circuits and Systems

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Ultra-low voltage nano-scale embedded RAMs are described, focusing on RAM cells and peripheral circuits. First, challenges and trends of low-voltage RAM cells are discussed in terms of signal charge, signal voltage, and noise. In addition to ECC, power-supply controls to widen the voltage margin of cells, and a fully-depleted SOI to reduce V Tvariation are also investigated. Then peripheral circuits are explained in terms of leakage reduction and compensation for speed variations. Based on this, it is concluded that ultra-low voltage RAMs cannot be achieved without reducing speed variations caused by variations in V T , thus resulting in a further need for compensation circuits and new devices with reduced V T variation.

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A case of autoimmune pancreatitis found by the onset of obstructive jaundice

Cited by 2 publications

References 0 publications

Low-voltage limitations of deep-sub-100-nm CMOS LSIs

Low-voltage limitations of deep-sub-100-nm CMOS LSIs

Ultra-Low Voltage Nano-Scale Embedded RAMs

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