Low-voltage limitations of deep-sub-100-nm CMOS LSIs

Abstract

Deep-sub-100-nm CMOS LSIs using a bulk CMOS device and a planar double-gate FD-SOI device are compared in terms of the low-voltage limitation of RAM cells, sense amplifiers, and logic gates. The limitation strongly depends on the ever-larger V T variation, especially in SRAM cells and logic gates, and is improved by the FD-SOI. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: High-V DD bulk CMOS LSIs for low-cost low-standby-current applications, and low-V DD FD-SOI LSIs for low-power applications.