A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory

Vijaykumar, Nandita; Jain, Abhilasha; Majumdar, Diptesh; Hsieh, Kevin; Pekhimenko, Gennady; Ebrahimi, Eiman; Hajinazar, Nastaran; Gibbons, Phillip B.; Mutlu, Onur

doi:10.1109/isca.2018.00027

Cited by 40 publications

(26 citation statements)

References 112 publications

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“…In practice, there might be data that do not need to be protected from speculative side-channel attacks, significantly limiting the number of speculative accesses that need to be delayed or predicted. Vijaykumar et al [54] have already proposed a solution for tagging memory regions that can be used exactly for this purpose, assuming that the sensitive data regions have been identified by the programmer.…”

Section: Future Workmentioning

confidence: 99%

Efficient invisible speculative execution through selective delay and value prediction

Sakalis

Kaxiras

Ros

et al. 2019

Proceedings of the 46th International Symposium on Computer Architecture

110

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Speculative execution, the base on which modern high-performance general-purpose CPUs are built on, has recently been shown to enable a slew of security attacks. All these attacks are centered around a common set of behaviors: During speculative execution, the architectural state of the system is kept unmodified, until the speculation can be verified. In the event that a misspeculation occurs, then anything that can affect the architectural state is reverted (squashed) and re-executed correctly. However, the same is not true for the microarchitectural state. Normally invisible to the user, changes to the microarchitectural state can be observed through various sidechannels, with timing differences caused by the memory hierarchy being one of the most common and easy to exploit. The speculative side-channels can then be exploited to perform attacks that can bypass software and hardware checks in order to leak information. These attacks, out of which the most infamous are perhaps Spectre and Meltdown, have led to a frantic search for solutions.In this work, we present our own solution for reducing the microarchitectural state-changes caused by speculative execution in the memory hierarchy. It is based on the observation that if we only allow accesses that hit in the L1 data cache to proceed, then we can easily hide any microarchitectural changes until after the speculation has been verified. At the same time, we propose to prevent stalls by value predicting the loads that miss in the L1. Value prediction, though speculative, constitutes an invisible form of speculation, not seen outside the core. We evaluate our solution and show that we can prevent observable microarchitectural changes in the memory hierarchy while keeping the performance and energy costs at 11% and 7%, respectively. In comparison, the current state of the art solution, InvisiSpec, incurs a 46% performance loss and a 51% energy increase.

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Section: Future Workmentioning

confidence: 99%

Efficient invisible speculative execution through selective delay and value prediction

Sakalis

Kaxiras

Ros

et al. 2019

Proceedings of the 46th International Symposium on Computer Architecture

110

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“…However, our work finds that graph-dependent irregular access patterns prevent these schemes from correctly learning which cache blocks to preserve, rendering them deficient for the broad domain of graph analytics. Meanwhile, to accomplish the second task, recent work proposes pinning of high-reuse cache blocks in LLC to ensure that these blocks are not evicted [7]. However, we find that pinning-based schemes are overly rigid and result in sub-optimal utilization of cache capacity.…”

Section: Introductionmentioning

confidence: 90%

“…We appropriately scale the number of sampling sets and predictor table entries for a 16MB cache. XMem [7] is a pinning-based scheme, originally proposed for algorithms that benefit from cache tiling. A cache block, once pinned, cannot be evicted until explicitly unpinned by the software, usually done when the processing of a tile is complete.…”

Section: Methodology For Hardware Evaluationmentioning

confidence: 99%

“…Meanwhile, we observe that the reuse for elements of the Property Array, which are the prime target for LLC caching in graph analytics (Sec II-C), does not correlate with the PC because the same PC accesses hot and cold vertices alike. 3 Pinning-based schemes such as XMem [7] dedicate partial or full cache capacity by pinning high-reuse blocks to cache. Hardware ensures that the pinned blocks cannot be evicted by other cache blocks and thus are protected from cache thrashing.…”

Section: F Prior Hardware Schemesmentioning

confidence: 99%

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Domain-Specialized Cache Management for Graph Analytics

Faldu

Diamond

Grot

2020

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Graph analytics power a range of applications in areas as diverse as finance, networking and business logistics. A common property of graphs used in the domain of graph analytics is a power-law distribution of vertex connectivity, wherein a small number of vertices are responsible for a high fraction of all connections in the graph. These richly-connected, hot, vertices inherently exhibit high reuse. However, this work finds that state-of-the-art hardware cache management schemes struggle in capitalizing on their reuse due to highly irregular access patterns of graph analytics.In response, we propose GRASP, domain-specialized cache management at the last-level cache for graph analytics. GRASP augments existing cache policies to maximize reuse of hot vertices by protecting them against cache thrashing, while maintaining sufficient flexibility to capture the reuse of other vertices as needed. GRASP keeps hardware cost negligible by leveraging lightweight software support to pinpoint hot vertices, thus eliding the need for storage-intensive prediction mechanisms employed by state-of-the-art cache management schemes. On a set of diverse graph-analytic applications with large high-skew graph datasets, GRASP outperforms prior domain-agnostic schemes on all datapoints, yielding an average speed-up of 4.2% (max 9.4%) over the best-performing prior scheme. GRASP remains robust on low-/no-skew datasets, whereas prior schemes consistently cause a slowdown.

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“…Many semantic or other characteristics of data (e.g., compressibility, approximability, sparsity, criticality, access and security semantics, locality, latency vs. bandwidth sensitivity, privacy requirements, data types, error vulnerability) are invisible or unknown to modern hardware and thus need to be communicated or discovered. We believe efficient and expressive software/hardware interfaces and resulting cross-layer mechanisms, as exemplified by X-Mem (Expressive Memory) [52,53] and the Virtual Block Interface [56] as well as other works [54,55,57,58,107,116,11], are promising and critically-needed approaches to creating general-purpose data-aware architectures.…”

Section: Data-awarementioning

confidence: 97%

Intelligent Architectures for Intelligent Machines

Mutlu

2020

2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications' performance, efficiency and scalability are bottlenecked by data movement. In this invited special session talk, we describe three major shortcomings of modern architectures in terms of 1) dealing with data, 2) taking advantage of the vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent architecture should be designed to handle data well. We show that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) dataaware. We give several examples for how to exploit each of these principles to design a much more efficient and high performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising novel directions: 1) processing using memory, which exploits analog operational properties of memory chips to perform massively-parallel operations in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory controllers, the logic layer of 3D-stacked memory technologies, or memory chips to enable high memory bandwidth and low memory latency to near-memory logic. We discuss how to enable adoption of such fundamentally more intelligent architectures, which we believe are key to efficiency, performance, and sustainability. We conclude with some guiding principles for future computing architecture and system designs. This accompanying short paper provides a summary of the invited talk and points the reader to further work that may be beneficial to examine.

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A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory

Cited by 40 publications

References 112 publications

Efficient invisible speculative execution through selective delay and value prediction

Efficient invisible speculative execution through selective delay and value prediction

Domain-Specialized Cache Management for Graph Analytics

Intelligent Architectures for Intelligent Machines

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