A Cascode Miller-Compensated Three-Stage Amplifier With Local Impedance Attenuation for Optimized Complex-Pole Control

Tan, Min; Ki, Wing-Hung

doi:10.1109/jssc.2014.2364037

Cited by 93 publications

(85 citation statements)

References 16 publications

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“…15, both the 3-step and 4-step NCM amplifiers achieve comparable , and break the limit of largedrivability. Before we apply any dynamic-biasing SR-enhancement technique [28], [29], the of the 4-step NCM amplifier is still 2.2 higher than [22], but 1.2 , 1.47 , 5.8 and 9.79 lower than [24]- [27], respectively. [26] and [27] have better owing to the added SR helper and aggressively scaled compensation capacitors, respectively, whereas both have a limited -drivability range.…”

Section: Resultsmentioning

confidence: 97%

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Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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For better area and power efficiencies, rail-to-railoutput single-stage amplifiers are a potential replacement of their multi-stage counterparts, especially for display applications that entail massive buffer amplifiers in their column drivers. This paper describes a nested-current-mirror (NCM) technique for a single-stage amplifier to achieve substantial enhancements of DC gain, gain-bandwidth product (GBW) and slew rate (SR). Specifically, NCM is customizable for different mirror steps, and sub mirror ratios, to balance the performance metrics and capacitive-load ( ) drivability, avoiding any compensation passives while preserving a rail-to-rail output swing. Analytical treatments of the NCM technique in terms of performance limits and robustness reveal that the NCM amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) amplifier. Two prototypes, 3-step and 4-step NCM amplifiers, were fabricated in 0.18 m CMOS for systematic comparison with the DP amplifier. The former represents a robust design exhibiting 72 dB DC gain and 0.0028-0.27 MHz GBW over 0.15-15 nF with 80 phase margin (PM). The latter embodies an aggressive design attaining 84 dB DC gain and 0.013-1.24 MHz GBW over 0.15-15 nF with 62 PM. All amplifiers were sized for the same area (0.0013 mm ) and power (3.6 W).Index Terms-Area efficiency, CMOS, current mirror, DC gain, differential-pair (DP) amplifier, frequency compensation, gain-bandwidth product (GBW), low temperature polysilicon LCD, multi-stage amplifier, nested current mirror, rail-to-rail output swing, single-stage amplifier, slew rate (SR), stability.

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Section: Resultsmentioning

confidence: 97%

“…Unlike the multi-stage amplifiers, no bulky passives are entailed in our single-stage solutions. To allow a fair comparison with recent three-stage amplifiers [22]- [27], two figuresof-merit (FOMs) [5] that account for the impact of both power and area: and , are introduced. As summarized in Fig.…”

Section: Resultsmentioning

confidence: 99%

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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“…The approach extends recent solutions (originally developed for three-stage amplifiers) that adopt only one external Miller capacitor [15]- [20]. In particular, the single Miller capacitor compensation network exploits passive components only, as in [18], [19], and is implemented without using extra transistors, thus saving circuit complexity and power consumption. Moreover, as a distinctive feature of the proposed four-stage amplifier, the last three gain stages are implemented using the simplest common source topologies, thus entailing minimum transistors number so that the same (or even less) number of transistors than a three-stage amplifier are exploited.…”

Section: Introductionmentioning

confidence: 91%

“…In particular, we can apply the NMC or RNMC approaches [3], [10], [11], either with or without feedforward stages, and approaches with only one external Miller capacitor [15]- [21]. Moreover, among the latter group, a recently proposed methodology amenable for large capacitive loads, adds left half plane (LHP) zeros in the inner nodes thanks to passive [18], [19] or active components [20].…”

Section: A Multistage Compensation Networkmentioning

confidence: 99%

High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads

Grasso

Palumbo

Pennisi

2015

IEEE Trans. Circuits Syst. I

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Designing four-stage operational transconductance amplifiers (OTAs) is often considered a challenging task mainly because of the required non trivial frequency compensation procedure. In this study, starting from the simplest architecture (a differential stage cascaded by three common source stages) a high-performance OTA is demonstrated, outperforming all the (few) previous implementations. Thanks to the frequency compensation scheme and to the adoption of a slew-rate enhancer section, the solution is able to drive large capacitive loads as high as 1 nF, rivaling in terms of bandwidth and speed even with three-stage counterparts, traditionally credited to be better because of the less number of high-impedance nodes. The solution, fabricated in a 0.35-technology, occupies 0.014-with DC consumption of 170. It also achieves nearly 3-MHz gain bandwidth product while driving the 1-nF load with less than 0.5-1% settling time.

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“…After investigating various methodologies reported earlier [11]- [17], also considering some very recently designed novel methodologies [18]- [21], compensation methodologies can be combined broadly into two: first, Nested Miller [22]- [29] and the second is Reversed Nested Miller [30] [37]. To implement miller effect, to get proper splitting of poles, required PM and/or appropriate time for settling in both types methodologies, two capacitors are required for compensation.…”

Section: Network Used For Frequency Compensationmentioning

confidence: 99%

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Gupta¹,

Gupta²,

Baghel³

2018

IJET

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/√ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator's delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

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A Cascode Miller-Compensated Three-Stage Amplifier With Local Impedance Attenuation for Optimized Complex-Pole Control

Cited by 93 publications

References 16 publications

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

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