A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC

Lü, Jie; Zheng, Boyi; Flynn, Michael P.

doi:10.1109/jssc.2019.2938626

Cited by 26 publications

(8 citation statements)

References 6 publications

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“…However, the ΔΣ ADCs require high-performance operational transconductance amplifiers (OTAs), which are powerhungry and scaling unfriendly. To combine the benefits of both SAR and ΔΣ ADCs while obviating their drawbacks, several recent works proposed the concept of NS SAR ADCs [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26] . A NS-SAR ADC is conceptually illustrated in Fig.…”

Section: Noise-shaping (Ns) Sarmentioning

confidence: 99%

“…noise-shaping filters [16][17][18][19] . Comparing to close-loop amplifiers that require complete settling, the open-loop ones operate in incomplete settling mode to save the power consumption.…”

Section: J X Liu Et Al: Error Suppression Techniques For Energy-effic...mentioning

confidence: 99%

“…A limitation of the CIFF structure is that the NTF zero location directly asso-ciates with the filter quality, leading to a steep trade-off between noise-shaping effect and power efficiency. To overcome the limitation of CIFF structure, researchers proposed the error feedback (EF) structure [17][18][19] . The first EF implementation of NS-SAR is presented by Li et al [17] .…”

Section: J X Liu Et Al: Error Suppression Techniques For Energy-effic...mentioning

confidence: 99%

“…To overcome the limitation of CIFF structure, researchers proposed the error feedback (EF) structure [17][18][19] . The first EF implementation of NS-SAR is presented by Li et al [17] . Its signal flow diagram is depicted in Fig.…”

Section: J X Liu Et Al: Error Suppression Techniques For Energy-effic...mentioning

confidence: 99%

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Error suppression techniques for energy-efficient high-resolution SAR ADCs

Liu¹,

Tang²,

Shen³

et al. 2020

J. Semicond.

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The successive approximation register (SAR) is one of the most energy-efficient analog-to-digital converter (ADC) architecture for medium-resolution applications. However, its high energy efficiency quickly diminishes when the target resolution increases. This is because a SAR ADC suffers from several major error source, including the sampling kT/C noise, the comparator noise, and the DAC mismatch. These errors are increasing hard to address in high-resolution SAR ADCs. This paper reviews recent advances on error suppression techniques for SAR ADCs, including the sampling kT/C noise reduction, the noise-shaping (NS) SAR, and the mismatch error shaping (MES). These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.

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Section: Noise-shaping (Ns) Sarmentioning

confidence: 99%

Section: J X Liu Et Al: Error Suppression Techniques For Energy-effic...mentioning

confidence: 99%

Section: J X Liu Et Al: Error Suppression Techniques For Energy-effic...mentioning

confidence: 99%

Section: J X Liu Et Al: Error Suppression Techniques For Energy-effic...mentioning

confidence: 99%

See 2 more Smart Citations

Error suppression techniques for energy-efficient high-resolution SAR ADCs

Liu¹,

Tang²,

Shen³

et al. 2020

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…As digital signal processing techniques have matured, analog signals have been processed more efficiently and accurately to make them more accessible [1][2][3]. The first step in processing them is often to convert them to digital signals and then to bring the signal processing up to the level of digital signal processing [4][5][6]. Digital signal processing, which replaces analog signal processing, has many advantages, including high reliability, flexibility, and ease of implementation [7].…”

Section: Introductionmentioning

confidence: 99%

A ENOB 10.3 bit, 103 μW ON-CHIP CALIBRATION SAR ADC

Zheng

Yao

et al. 2023

J. Phys.: Conf. Ser.

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Across the board, the performance of ADCs has been under increasing scrutiny because of the rapid growth of portable electronic devices and biomedical sensors. As part of the sensor’s long-term work, its power consumption should also be as low as possible. Sensors benefit from SAR ADCs’ small size and low power consumption, making them an ideal fit for ADCs. To overcome the limitations of accuracy and linearity of ADCs caused by manufacturing process deviations, a 12-bit, 1 MS/s low-power SAR ADC based on 180 nm CMOS technology is presented. The front-end analog calibration system ensures the ADC is at its best. The design also includes low fan-in SAR logic to reduce the capacitive load on the comparator and increase the comparison speed. The layout area is 0.3 mm2, approximately 30% less than conventional products of the same process.

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The Evolution of Noise-Shaping Successive Approximation (SAR) ADC

Flynn

Lee

2023

Biomedical Electronics, Noise Shaping ADCs, and Frequency References

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A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC

Cited by 26 publications

References 6 publications

Error suppression techniques for energy-efficient high-resolution SAR ADCs

Error suppression techniques for energy-efficient high-resolution SAR ADCs

A ENOB 10.3 bit, 103 μW ON-CHIP CALIBRATION SAR ADC

The Evolution of Noise-Shaping Successive Approximation (SAR) ADC

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