A bus delay reduction technique considering crosstalk

Abstract

Recently, progress in shrinking CMOS process technology and increasing chip size has made interconnect delay a serious problem in deep micron LSI design. The interconnect delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch in opposite transient directions. This paper proposes an on‐chip bus delay reduction technique based on shifting the signal transition timing of adjacent wires. From an equation for the approximate bus delay, delay reduction can be achieved by applying the proposed technique to repeater‐inserted on‐chip buses. The result of SPICE simulation also shows that at most a 20% reduction of the total bus delay can be achieved. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 85(1): 24–31, 2002

Novel low-power bus invert coding methods with crosstalk detector

“…To compare our methods with the un-coded data bus, we simulate five different test files (i.e., the random data, image files, PPT files, MP3 files, and PDF files) to calculate the averages of coupling activity and switching activity, and the parameter. The parameter is set to 10, which is in agreement with previous papers (Vittal and Marek-Sadowska 1997, Hirose and Yasuura 2000, Duan et al 2001, Victor and Keutzer 2001, Ayoub and Orailoglu 2005, Ghoneima et al 2006, Khan et al 2006, Lyuh and Kim 2006. In this article, the BI (Micea 1995) PBI (Youngsoo , 2001 Simple parameter ranges from 1 to 5.…”

“…The signal transitions on 3-bit lines are classified into five types, as shown in Table 1. We apply Equation (2) as follows (Hirose and Yasuura 2000):…”

“…For a 2-bit bus, the methods in Ayoub and Orailoglu (2005), Lyuh and Kim (2006), Huang and Hwang (2004), Kim et al (2000), Macchiarulo et al (2001), and Zhan et al (2002) are applied to encode data buses. Similarly, there are many well-known bus coding technologies (Hirose and Yasuura 2000, Macchiarulo et al 2002, Khan et al 2006, Tu et al 2006 applied to 3-bit buses. For example, Hirose and Yasuura (2000) apply repeater technology to reduce total bus delay.…”

“…Similarly, there are many well-known bus coding technologies (Hirose and Yasuura 2000, Macchiarulo et al 2002, Khan et al 2006, Tu et al 2006 applied to 3-bit buses. For example, Hirose and Yasuura (2000) apply repeater technology to reduce total bus delay. Khan et al (2006) use the alternate complement value and shield wires to reduce crosstalk effects.…”

“…,Victor and Keutzer (2001),Hirose and Yasuura (2000),Lyuh and Kim (2006),Khan et al (2006),Vittal and Marek-Sadowska (1997),Ghoneima et al (2006),Duan et al (2001),Zhan et al (2002),Tu et al (2006), …”