A Buck-Derived Topology With Improved Step-Down Transient Performance

Abstract

The slew rate of the inductor current is limited by the inductance value and the voltage across the inductor. In a buck converter, when the controller is saturated, the voltage across the inductor during a step-up load transient is V in − V ou t , while during a step-down load transient, it is −V ou t . Thus, a buck converter with a large conversion ratio offers asymmetrical step-up and step-down transients. Since the rate of fall of the inductor current is much slower than the rate of rise of the inductor current, the step-down transient lasts longer than the step-up transient for the same change in the load current. The step-down slew rate can be increased by reducing the inductance, but it results in higher inductor current ripple, and hence, higher losses in the power converters. In this paper, we present a novel topology for improving the step-down load transients without reducing the inductance value. The scheme operates only during load transients and restores to the normal operating conditions during steady-state operation. It provides reduced voltage overshoots and faster settling times in output voltage during such transients. The proposed scheme is tested on a 1-V/12-A buck converter switching at 1 MHz, and the experimental results are presented.Index Terms-Current-mode control, high slew rates, voltage regulator module (VRM).

Output characteristics of step-down (Buck) power converter

“…The most representative example of such a load is a processor in modern computer equipment. Actually, the supply voltage of such processors are about or below 1.0 V, the current is typically over 100 A, with the slew rate approaching 300 A/µs [4,5]. For the numbers given above, the equivalent load resistance is below 10 mΩ and the output resistance of converter should be substantially lower, to ensure a good efficiency.…”

“…The first, typical way is the sophisticated design of control loops in converters [6][7][8][9]13]. The second way is based on modifications of the basic structure of the power stage [5]. The amount of the literature on the subject is extensive and the references listed above may serve only as examples.…”

Reduction of equivalent series inductor effect in delay-ripple reshaped constant on-time control for buck converter with multi-layer ceramic capacitors

“…According to the steady-state waveforms in Fig. 4 if the ESL effect is ignored, the voltage difference should be zero after one switching period as expressed in (4). The switching period T S W is the summation of the T ON and the T OFF , which are the on-time and the off-time, respectively…”

On the extraction of input and output impedance of PWM DC-DC converters

“… Sophisticated design of control loops in the converter [13,14,15,16]  Modifications of the basic structure of the power stage [17][18]. The starting point of the first method is the precise description of the converter, in particular the use of accurate formulas for open-loop output impedance.…”