A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-μ#x3BC;m SOI CMOS Technology

Cho, Moon-Kyu; Kim, Jeong‐Geun; Baek, Dong‐Hyun

doi:10.4218/etrij.13.0112.0534

Cited by 10 publications

(6 citation statements)

References 6 publications

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“…The reference and attenuation states of the π-type attenuation cell with shunt capacitance are shown in Figure 9b,c, respectively. The transmission coefficients S 21 can be calculated from the transmission matrix of the two different states, as shown in ( 16) and (17).…”

Section: π-Type Attenuation Cell With Shunt Capacitorsmentioning

confidence: 99%

“…As shown in Figure 1b, this attenuation cell divides th erence and attenuation states into two separate paths capable of increasing the deg freedom for a phase adjustment and obtaining small phase variation. However, th and IL of this cell are larger [11,17]. π-type attenuation cells can achieve large atten levels and small IL, while the large phase variation of the conventional π-type atten cell makes it unsuitable for wideband systems [4,6].…”

Section: Introductionmentioning

confidence: 99%

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A C/X/Ku/K-Band Precision Compact 6-Bit Digital Attenuator with Logic Control Circuits

Zeng

Yuan

et al. 2022

Electronics

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This paper proposes a C/X/Ku/K band 6-bit digital step attenuator (DSA) which employs a variety of improved attenuation cells to achieve a wide bandwidth, stable amplitude variation, stable phase variation, and small area. In this paper, the improved T-type, π-type, and switched-path type topologies are analyzed theoretically and applied to different attenuation values to achieve the optimal attenuator performance. In addition, in order to reduce the complexity and to improve the stability of the overall radar system, the logic control circuit is integrated in the DSA chip in this paper. Finally, the proposed attenuator is implemented in 0.15μm GaAs technology, which has a maximum attenuation range of 31.5 dB with 0.5 dB steps. The proposed DSA exhibits a root-mean-square (RMS) attenuation error of less than 0.15 dB and an RMS phase error of less than 3°, at 4–24 GHz. The insertion loss (IL) and the area of the DSA are 4.3–4.5 dB and 1.5 mm × 0.4 mm, respectively. Benefiting from the improvements of the attenuation cells and the characteristic of GaAs technology with strong resistance to radiation and power processing capability, the proposed DSA is suitable for spaceborne radar systems.

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Section: π-Type Attenuation Cell With Shunt Capacitorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A C/X/Ku/K-Band Precision Compact 6-Bit Digital Attenuator with Logic Control Circuits

Zeng

Yuan

et al. 2022

Electronics

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“…Simultaneously, when Z 0 ¼ 50 Ω and A ¼ À1 dB, R sT and R pT are 2.88 Ω and 433.34 Ω, respectively. Therefore, the 1 dB attenuator also adopts the simplified T-type topology [26]. The simplified T-type unit has trouble to achieve the 2 dB attenuation since the series resistance is 5.73 Ω, which cannot be ignored.…”

Section: Circuit Descriptionsmentioning

confidence: 99%

“…The third scheme is the distributed attenuator [7,21,22,23,24,25], while it still has troubles in the attenuation ranges since it demands many transmission lines and hence consumes a large chip area [21]. Moreover, previous works have rarely discussed the amplitude/phase calibration issues of the attenuator [14,15,20,21,22,26], since numerous components in the PI/T type attenuator and transmission lines in the distributed attenuator are particularly troublesome to realize the calibration.…”

Section: Introductionmentioning

confidence: 99%

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

Ding

Chen

et al. 2019

IEICE Electron. Express

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A mm-wave 5-bit digital attenuator with low RMS (root mean square) amplitude error and low phase variation is presented in 65 nm CMOS. The attenuator combines the PI/T-type topology with embedded switches and PI-type topology with the SPDT (single-pole-double-throw) switches to alleviate the insertion loss issue of the conventional PI/T-type topology with embedded switches in mm-wave frequency band, and achieves high attenuation range while maintaining compact chip size. The amplitude/phase calibration technique is proposed to reduce the RMS amplitude error/phase variation and improve the circuit robustness. The presented attenuator has been integrated in a Ka-band phased-array transmit front-end module and achieves 15.5 dB attenuation coverage with the step of 0.5 dB. The RMS amplitude error and RMS phase variation are 0.13-0.48 dB and 1.24-2.08°across 25-35 GHz, respectively. Especially, the proposed attenuator could achieve the RMS amplitude error of 0.13-0.25 dB if the operation frequency is limited to 26.9-31.4 GHz. The core chip size is 434 µm × 360 µm.

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“…The 6-bit DSA circuit was designed using the switched Ttype topology, which is adequate for a small chip area and low insertion loss [9]. Figure 5A shows the schematic of the high attenuation states of 2 dB, 4 dB, and 8 dB including a phase-compensation capacitor (C P ).…”

Section: -Bit Digital Step Attenuatormentioning

confidence: 99%

CMOS true-time delay IC for wideband phased-array antenna

2018

Self Cite

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This paper presents a true‐time delay (TTD) using a commercial 0.13‐μm CMOS process for wideband phased‐array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7‐bit TTD circuit, and a 6‐bit digital step attenuator (DSA) circuit. The T‐type attenuator with a low‐pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time‐delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz–18 GHz. The maximum time delay of 198 ps with a 1.56‐ps step and the maximum attenuation of 31.5 dB with a 0.5‐dB step are achieved at 2 GHz–18 GHz. The RMS time‐delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz–18 GHz. An output P1 dB of <−0.5 dBm is achieved at 2 GHz–18 GHz. The chip size is 3.3 × 1.6 mm2, including pads, and the DC power consumption is 370 mW for a 3.3‐V supply voltage.

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A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-μ#x3BC;m SOI CMOS Technology

Cited by 10 publications

References 6 publications

A C/X/Ku/K-Band Precision Compact 6-Bit Digital Attenuator with Logic Control Circuits

A C/X/Ku/K-Band Precision Compact 6-Bit Digital Attenuator with Logic Control Circuits

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

CMOS true-time delay IC for wideband phased-array antenna

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