A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip

Abbasi, Morteza; Kjellberg, Torgil; Graauw, Anton de; Heijden, E. van der; Roovers, R.; Zirath, Herbert

doi:10.1109/rfic.2010.5477384

Cited by 25 publications

(5 citation statements)

References 11 publications

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“…Obviously, by increasing by a factor K the number of PA blocks, taking into account also the extra circuit needed to combine their power towards the transmitter antenna, the total area and power consumption increases by a factor higher than K while the maximum transmitter power increases by a factor below K. In our experiments, the power combination mechanism can be useful to meet transmitted power of 11.8 mW and 17.9 mW by combining 2 or 4 basic PA blocks respectively. Comparing these results vs. recent state of art [14,15] it is worth noting that the above power levels refer to OP1dB and hence are obtained with a very high linearity (less than 1 dB compression vs. the ideal amplifier response). In state of art of mmWave CMOS amplifier for 60 GHz consumer applications such high power levels are typically obtained as maximum saturated power with higher distortions.…”

Section: Introductionsupporting

confidence: 59%

System-Level Analysis for Integrated Power Amplifier Design in mmWave Consumer Wireless Communications

Saponara

Neri

2017

Lecture Notes in Electrical Engineering

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System-level specifications for the design of integrated power amplifiers in mmWave wireless communications are derived in the paper. To this aim emerging standards for consumer applications such as wireless ultra-high definition (UHD) multimedia streaming or Gbit wireless LAN are considered (WirelessHD, WiGig, ECMA387, IEEE.802.11.ad, IEEE802.15.3c and upcoming 5G). A power amplifier design in 65 nm CMOS Silicon on Insulator (SOI) technology, targeting a 9 GHz UWB window from 57 to 66 GHz, is also proposed. To increase the power delivered to the antenna up to 18 mW, being still in the limit of maximum 1dB compression point, multiple PA cores have been combined through a Wilkinson power combiner, but other solutions can be also explored for a better power efficiency and linearity.

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Section: Introductionsupporting

confidence: 59%

System-Level Analysis for Integrated Power Amplifier Design in mmWave Consumer Wireless Communications

Saponara

Neri

2017

Lecture Notes in Electrical Engineering

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“…The output power and gain, on the other hand, are considerably lower than the ones achieved in this work. 60 GHz PAs in 45-nm CMOS are presented in [20][21][22][23][24]. While [20], [21] and [23] achieve higher gains, but inferior output powers and PAE; [24] provides higher output powers but the gain is limited to 6 dB and the PA E remains inferior to 10%.…”

Section: Comparison With the State-of-the-artmentioning

confidence: 99%

12 dBm OCP1dB Millimeter-wave 28 nm CMOS Power Amplifier using Integrated Transformers

Leite¹,

Kerhervé²,

Belot³

2020

JICS

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This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and uses one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns are sized to provide low insertion losses and high common-mode rejection rate (CMRR) as well as integrating the input and output matching networks. The designed baluns achieve minimum insertion losses better than 0.8 dB and CMRR superior to 27 dB. The output-stage transistors have a measured 1 dB output compression point (OCP1dB) of 10.2 dBm, 10.1 dB gain and peak power added efficiency (PAE) as high as 35%. Thanks to the transformers, the PA presents a compact implementation, occupying only 0.037 mm² on silicon. The fabricated PA achieves 12 dBm OCP1dB, 15.3 dB gain and peak PAE better than 20%.

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“…To this aim, several mm-wave amplifier designs in silicon or III-V technologies have been proposed at state-of-art. [17][18][19][20][21][22][23][24][25][26] Most of them miss a system-level analysis of 5G specifications, and therefore do not allow exploiting all the capabilities envisaged for this new standard, such as: i) operating frequencies around the 60 GHz band for very dense cell deployment and transceivers with a wideband front-end (9 GHz-wide, see Fig. 1), to enable several channelization strategies and flexible reception of multi-format multi-Gb/s signals; ii) integration at such high frequencies of all active and passive devices, including even the antenna for short-range links, covering distances up to tens of meters, using CMOS silicon technologies for low-cost and compact 5G terminals;…”

Section: Evolution Of Lte-a As a Support For Mtc In 5gmentioning

confidence: 99%

“…22 but using a lower supply voltage, 1.2 V instead of 2 V in Ref. 22. Using in our case for the PA the same supply voltage of all the other blocks, including also the baseband and digital circuitry, reduces the overall system complexity avoiding extra DC-DC converter in the power management unit.…”

Section: Mm-wave Linear Pa For 5g Communicationsmentioning

confidence: 99%

Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G

Saponara

Giannetti

Neri

2016

J CIRCUIT SYST COMP

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This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to derive transceiver design specifications. Being 5G still in pre-standardization phase, a few currently used standards (ECMA-387, IEEE 802.15.3c, and LTE-A) are taken into account as the reference for the signal format. Following a top-down flow, this work presents the design in 65nm CMOS SOI and bulk technologies of the key blocks of a fully integrated transceiver: low noise amplifier (LNA), power amplifier (PA) and on-chip antenna. Different circuit topologies are presented and compared allowing for different trade-offs between gain, power consumption, noise figure, output power, linearity, integration cost and link performance. The best configuration of antenna and LNA co-design results in a peak gain higher than 27dB, a noise figure below 5dB and a power consumption of 35mW. A linear PA design is presented to face the high Peak to Average Power Ratio (PAPR) of multi-carrier transmissions envisaged for 5G, featuring a 1dB compression point output power (OP1dB) of 8.2dBm. The delivered output power in the linear region can be increased up to 13.2dBm by combining four basic PA blocks through a Wilkinson power combiner/divider circuit. The proposed circuits are shown to enable future 5G connections, operating in a mm-wave spectrum range (spanning 9GHz, from 57GHz to 66GHz), with a data-rate of several Gb/s in a short-range scenario, spanning from few centimeters to tens of meters

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A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip

Cited by 25 publications

References 11 publications

System-Level Analysis for Integrated Power Amplifier Design in mmWave Consumer Wireless Communications

System-Level Analysis for Integrated Power Amplifier Design in mmWave Consumer Wireless Communications

12 dBm OCP1dB Millimeter-wave 28 nm CMOS Power Amplifier using Integrated Transformers

Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G

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