A broad strategy to detect crosstalk faults in network-on-chip interconnects

Botelho, Mariza; Kastensmidt, Fernanda Lima; Lubaszewski, Marcelo; Cota, Érika; Carro, Luigi

doi:10.1109/vlsisoc.2010.5642677

Cited by 10 publications

(4 citation statements)

References 15 publications

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“…Reference [7] discloses the model of crosstalk faults that is referred to as the Maximum Aggressor Fault Model (MAFM) and is commonly used in many scientific studies including [37], [6], [11] that deal with testing of crosstalk faults. The model assumes that at each specific moment of time only one interconnection within the network is the victim line and all other ones can act as aggressors.…”

Section: Test Sequences Dedicated To Stimulate Crosstalk Faultsmentioning

confidence: 99%

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Garbolino

2015

International Journal of Electronics and Telecommunications

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Abstract-The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence. This study is dedicated to an innovative structure of a test pattern generator aimed at stimulation of crosstalk faults that may happen to bus-type connections. The fully scalable and synthesizable model of such a TPG unit has been developed in the VHDL language. The model was subjected to thorough investigations with regard to the length of the output test sequence and the associated hardware overhead. KeywordsThe TPG disclosed in this study is an improved option of the solution already described in [9]. The new design of the TPG benefits from reduction in length of the shift register and alteration of the test vector counter. These measures made it possible to achieve a TPG structure that highlights with less hardware overhead and much higher operation frequency than the solution presented in [9].

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Section: Test Sequences Dedicated To Stimulate Crosstalk Faultsmentioning

confidence: 99%

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Garbolino

2015

International Journal of Electronics and Telecommunications

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show abstract

“…Reference [7] discloses the model of crosstalk faults that is referred to as Maximum Aggressor Fault Model (MAFM) and is commonly used in many scientific studies including [22], [6], [9] that deal with testing of crosstalk faults. The model assumes that at each specific moment of time only one interconnection within the network is the victim line and all other ones can act as aggressors.…”

Section: Crosstalk Faultsmentioning

confidence: 99%

Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections

Garbolino

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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The paper reveals a completely new and original structure of a Test Pattern Generator (TPG) dedicated for detection of crosstalk faults that may happen to bus-type connections between individual cores of a System on a Chip (SoC). The TPG is designed to generate either the MAFM (Maximum Aggressor Fault Model) sequence of test vectors or the XMAFM (eXtended Maximum Aggressor Fault Model) one, which guarantees that all possible crosstalk faults of the capacitive nature that may occur between individual lines of a digital bus are detectable. The study presents the synthesizable and parameterized (scalable) model of the mentioned TPG developed in the VHDL language. The proposed TPG structures feature with high working frequency and good scalability in terms of both the hardware overhead and length of the output test sequence. In addition, the TPG structure enables easy integration of the solution with Design for Testability solutions, such as a scan path, a wrapper designed in compliance with the IEEE 1500 standard or with the Built-in Self-Test circuits that might be already implemented in IP cores embedded in a SoC. In such a case the area overhead of the proposed structure never exceeds several dozens of equivalent gates, which is a negligible amount.

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“…Diferentes soluções para provimento de tolerância a faltas em NoCs são descritas na literatura. Em [6], é apresentada uma estratégia de teste global para detectar faltas decorrentes de crosstalk em NoCs com topologia em malha. Em [7], foi proposto um novo mecanismo para a detecção de erros de roteamento em uma NoC adaptativa/reconfigurável.…”

Section: Introductionunclassified

Mechanisms to Provide Fault Tolerance to a Network-on-Chip

Pereira

Melo

Bezerra

et al. 2017

IEEE Latin Am. Trans.

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The constant reduction in the components size of integrated circuits, as well as higher operating frequencies, increases the vulnerability to internal and external noise sources. These noises can cause a failure in any component, affecting the operation of the system as a whole. Systems-on-Chip with dozens of cores are based on Networks-on-Chip (NoCs), and require networks that are able to detect and prevent a fault in leading to a system failure and an application malfunction. In this context, this work aims at evaluating solutions to increase the reliability and availability of a NoC by adding mechanisms for error detection and correction. Spatial and information redundancy techniques were applied in order to protect the network against Single Event Upset faults. The applied techniques ensured the correct operation of the NoC in the presence of faults, with low impact to the performance and with acceptable silicon costs.

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A broad strategy to detect crosstalk faults in network-on-chip interconnects

Cited by 10 publications

References 15 publications

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections

Mechanisms to Provide Fault Tolerance to a Network-on-Chip

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