A Bottom-Gate Indium-Gallium-Zinc Oxide Thin-Film Transistor With an Inherent Etch-Stop and Annealing-Induced Source and Drain Regions

Abstract

The resistivity of an indium-gallium-zinc oxide (IGZO) thin film was found to depend on not only the conditions of its thermal annealing but also the oxygenpermeability of the cover film during the heat treatment. Based on this observation, a technology for constructing a bottom-gate IGZO thin-film transistor with annealing-induced source and drain (S/D) regions is proposed and demonstrated. The S/D and channel regions with this device architecture are capped, respectively, by impermeable and permeable covers. During a subsequent heat treatment in an oxidizing atmosphere, the resistivity of the S/D regions is greatly reduced; while the channel region, being exposed to the oxidizing atmosphere through the permeable cover, retains its highly resistive character. The permeable cover protects the channel region by serving additionally as an inherent back-channel etch-stop during the etching of the impermeable cover. No patterning is needed to realize this etch-stop, implying a lower manufacturing cost.

An oxidation-last annealing for enhancing the reliability of indium-gallium-zinc oxide thin-film transistors

“…In this work, MO TFTs with thermally induced source/ drain (S/D) regions 11 were constructed. The effects of annealing in an inert or oxidizing atmosphere on device reliability were compared using a single TFT, thus eliminating the confounding effects of the statistical variation alluded to earlier.…”

“…For a TFT with thermally induced S/D regions, the "activation" of the S/D regions and the oxidizing annealing of the channel region are accomplished simultaneously during the post-metallization oxidizing thermal treatment. 11 The duration of the treatment is constrained by the desire to achieve an adequately low resistance in the S/D regions and a sufficient reduction in the population of V O in the channel. The dependence of both the stress-induced DV on after 10 000 s NBIS (the most severe of the 4 stress conditions) and the normalized S/D sheet resistance on the activation annealing time at 400 C in O 2 was investigated and is plotted in Fig.…”

P‐18: Student Poster: Non‐Oxidizing Pre‐Annealing for Enhanced Fluorination of an Indium‐Gallium‐Zinc Oxide Thin‐Film Transistor

“…Finally, elevated-metal metaloxide (EMMO) TFTs were realized by annealing at 400 °C in O2 for 4 hrs. In an EMMO TFT, the portion of the IGZO exposed to the oxidizing atmosphere through the gas-permeable SiOx forms the intrinsic active channel region, resulting from the passivation of the donor-defects (9). The portions of the IGZO covered under the gasimpermeable Al/Mo electrodes are converted to conductive, annealing-induced S/D regions.…”

24.3: Short‐Channel Indium‐Gallium‐Zinc Oxide Thin‐Film Transistor Enabled by Thermal Dehydrogenation and Oxidizing Defect‐Suppression

“…This behavior is conventionally dubbed the "short channel effect (SCE)". The shift becomes noticeable for L < 10 µm, reflecting an increased mobile charge carrier density [7], [8] in the channel region. Such apparent SCE is more severe in the SiN y -containing TFTs, with the transistor essentially shorted at L = 2 µm.…”

“…For conventional back-channel-etched (BCE) and the etch-stop (ES) architectures bottom-gate IGZO TFTs, the device performance is usually compromised for BCE TFTs because of damage to the channel layer or the device footprint is larger for ES TFTs because of the longer channel length (L). Enabled by the annealing-induced formation of conductive source/drain (S/D) regions in IGZO [7], [8], an elevated-metal metal-oxide (EMMO) architecture offering an ES-like protection of the channel region while maintaining a BCE-like small footprint has recently been proposed [9], [10]. Though an EMMO TFT ( Fig.…”