A BJT-Based Temperature-to-Digital Converter With ±60 mK ( $3~\sigma$ ) Inaccuracy From −55 °C to +125 °C in 0.16-μm CMOS

Abstract

This paper presents a precision CMOS temperature-to-digital converter (TDC), which senses the temperature-dependent base-emitter voltage of substrate PNPs. Measurements on 20 samples from one batch show that it achieves an inaccuracy of ±60mK (3σ) from −55 • C to +125 • C, after a single room temperature trim. This state-of-the-art result is mainly due to the extensive use of dynamic error cancellation techniques to generate the PNP's collector currents, thus minimizing the spread in their base-emitter voltages, together with a digital PTAT trim to correct for the spread in the PNP's saturation currents. The effect of process variation on the TDC's inaccuracy was investigated by measuring 80 samples from 3 different batches. With the same calibration parameters, they exhibit a maximum untrimmed inaccuracy of ±2 • C (3σ) from −55 • C to +125 • C. This drops to ±100mK (3σ) after a single point trim. The proposed TDC thus reduces calibration costs by obviating the need for batchspecific calibration parameters, which would otherwise require the multi-point calibration of several samples. The effect of the PNP's current-gain β was also investigated with the help of a novel βdetection circuit. Implemented in 0.16µm CMOS, the TDC occupies 0.16mm 2 and draws 4.6µA from 1.5 to 2V supply voltages. It achieves a resolution FoM of 7.8pJ • C 2 , and a state-of-the-art supply sensitivity of 0.01 • C/V.

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