A BIST scheme for the detection of path-delay faults

A low-speed BIST framework for high-performance circuit testing

“…In the past, a number of papers have been published with regard to BIST for detecting delay faults [15][16][17][18][19]. Most efforts have been confined to generating the required two-pattern tests for detecting delay faults.…”

“…Here, hardware is designed which generates sequences in which the test pairs (initialisation and propagation vector) are embedded [16]. The key elements in these generators are special Linear Feedback Shift Registers (LFSR) [17] or Multiple Input Signature Registers (MISR) [18]. Although rarely discussed, the evaluation of the responses can be carried out in a similar way as in "conventional" digital BIST approaches using signature analysers.…”