A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

Kuo, J.B.; Su, Kuan-Wei; Lou, J.H.

doi:10.1109/4.400440

Cited by 4 publications

(2 citation statements)

References 18 publications

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“…Many different implementations for multipliers and dividers exist, and data integrity and fault detection probability depend on the particular design implementation. In this section, we consider a parallel array multiplier [32], Wallace Tree multiplier [33] and a datapath of SRT divider [34] In a 12-bit array multiplier and 8-bit Wallace Tree multiplier as examples, we randomly selected a node in the multiplier and injected a stuck-at fault into the node. For example, there are 1176 nodes in the 12-bit array multiplier.…”

Section: Multiplier and Dividermentioning

confidence: 99%

ED/sup 4/I: error detection by diverse data and duplicated instructions

Mitra

McCluskey

2002

IEEE Trans. Comput.

218

103

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Errors in computing systems can cause abnormal behavior and degrade data integrity and system availability. Errors should be avoided especially in embedded systems for critical applications. However, as the trend in VLSI technologies has been towards smaller feature sizes, lower supply voltages, and higher frequencies, there is a growing concern about temporary errors as well as permanent errors in embedded systems; thus, it is very essential to detect those errors. Software Implemented Hardware Fault Tolerance (SIHFT) is a low-cost alternative to hardware fault tolerance techniques for embedded processors: it does not require any hardware modification of Commercial Off-The-Shelf (COTS) processors. ED 4 I is a SIHFT technique that detects both permanent and temporary errors by executing two "different" programs (with the same functionality) and comparing their outputs. ED 4 I maps each number, x, in the original program into a new number x′, and then transforms the program so that it operates on the new numbers so that the results can be mapped backwards for comparison with the results of the original program. The mapping in the transformation of ED 4 I

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Section: Multiplier and Dividermentioning

confidence: 99%

ED/sup 4/I: error detection by diverse data and duplicated instructions

Mitra

McCluskey

2002

IEEE Trans. Comput.

218

103

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“…[4] provided a closed form design optimization through transistor reordering for minimum expected dynamic power dissipation in the internal nodes of the MOSFET chain of a CMOS NAND gate. In this paper, we have focused on the dynamic BiCMOS logic gates (reported by several authors, [5,7,9]), and, have proposed improved transistor reordered structures based on a deterministic (rather than probabilistic) power dissipation measure. Small reduction in the gate delay-time is also achieved by this transistor reordering.…”

Section: Introductionmentioning

confidence: 99%

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Hasan

Wahab

2002

VLSI Design

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This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

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Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems

Kuo

Chiang

1995

IEEE Trans. Circuits Syst. I

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A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

Cited by 4 publications

References 18 publications

ED/sup 4/I: error detection by diverse data and duplicated instructions

ED/sup 4/I: error detection by diverse data and duplicated instructions

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems

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