A BiCMOS dynamic defuzzify circuit for VLSI implementation of large-scale fuzzy logic controllers

A 1.5 V BiCMOS dynamic logic circuit using a "BiPMOS pull-down" structure for VLSI implementation of full adders

“…(Note: Details on race problems in cascading dynamic logic gates are described in [6], [7].) In the BiCMOS dynamic circuits with the BiPMOS pull-up structure, N-type and P-type BiCMOS dynamic cells have been placed alternatively to avoid race problems [6]- [12]. In addition, since each N-type or Ptype BiCMOS dynamic cell is an inverter, pairs of complementary input signals are needed-this may complicate the circuit design.…”