A Bank-Wise DRAM Power Model for System Simulations

Mathew, Deepak M.; Zulian, Éder F.; Kannoth, Subash; Jung, Matthias; Weis, Christian; Wehn, Norbert

doi:10.1145/3023973.3023978

Cited by 10 publications

(5 citation statements)

References 18 publications

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“…To study the behavior of real DRAM chips under reduced voltage, we build an FPGAbased infrastructure based on SoftMC [109], which allows us to have precise control over the DRAM modules. This method was used in many previous works [57,109,151,152,159,160,161,167,168,188,190,192,210,224,287] as an effective way to explore different DRAM characteristics (e.g., latency, reliability, and data retention time) that have not been known or exposed to the public by DRAM manufacturers. Our testing platform consists of a Xilinx ML605 FPGA board and a host PC that communicates with the FPGA via a BETWEEN LATENCY AND VOLTAGE IN DRAM PCIe bus (Figure 7.2).…”

Section: Experimental Methodologymentioning

confidence: 99%

Understanding and Improving the Latency of DRAM-Based Memory Systems

Chang

2017

Preprint

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Section: Experimental Methodologymentioning

confidence: 99%

Understanding and Improving the Latency of DRAM-Based Memory Systems

Chang

2017

Preprint

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“…We employ the DRAM simulation framework DRAM-Sys [30], [31] and the power modeling tool DRAM-Power [32], [33] to evaluate the impact of refresh on the performance and energy of DRAMs while running realistic applications. We employ trace-based simulation approach for the majority of experiments due to the fast simulation time, but also validate our results against full-system simulations for some applications.…”

Section: Impact Of Elevated Temperatures On Applications a Simulation Setupmentioning

confidence: 99%

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling

et al. 2021

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Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TECbased cooling ensures that the maximum temperature of all DRAM chips is always below 85°C despite that the original on-chip temperature (i.e., in the absence of our TEC based cooling) goes beyond 120°C.

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“…Figure 3.10 shows the closed loop simulation. This simulation loop consists of (1) DRAM and gem5 Core Models [5,18], (2) a DRAM power model [6,29], which uses either parameters from datasheets, or real measurements [13,15], (3) a thermal model based on 3D-ICE [38], and (4) a DRAM retention error model [42].…”

Section: Temperature Vs Reliabilitymentioning

confidence: 99%

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Jung

Weis

Wehn

2020

A Journey of Embedded and Cyber-Physical Systems

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Dynamic random access memories (DRAMs) are key components in all computing systems that require large working memory. Due to the strong increase in data volume in many embedded applications, such as machine learning, image processing, autonomous systems, etc., DRAMs largely impact the overall system performance and power consumption. In many of these applications, the overall system performance is often limited by the memory bandwidth or latency and not by the computation itself. Due to the dynamic storage scheme of DRAMs and shrinking technology nodes, reliability is also a major concern in current and future DRAMs. Therefore, new challenges arise, which we will discuss in this chapter. The most important metrics, which are typically considered for DRAM subsystems (especially in the high-performance computing (HPC) domain), are bandwidth, latency, and capacity. However, in the context of embedded systems it requires to consider further metrics, such as power, temperature, reliability, safety, and security. In the following we will highlight these challenges and refer to some of our recent contributions, which tackle these challenges.

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A Bank-Wise DRAM Power Model for System Simulations

Cited by 10 publications

References 18 publications

Understanding and Improving the Latency of DRAM-Based Memory Systems

Understanding and Improving the Latency of DRAM-Based Memory Systems

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

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