A Background Calibration Technique to Control the Bandwidth of Digital PLLs

Mercandelli, Mario; Grimaldi, Luigi M. E.; Bertulessi, Luca; Samori, Carlo; Lacaita, A.L.; Levantino, Salvatore

doi:10.1109/jssc.2018.2866454

Cited by 15 publications

(9 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The loop bandwidth of ADPLL extensively impacts the output jitter performance 13 of ADPLL. The relationship between loop bandwidth and gain is given by 13

G_{loop} ((), Z) goodbreak= \frac{{NK}_{TDC} K_{DCO}}{1 - Z^{- 1}} * ((), α goodbreak+ \frac{β}{1 - Z^{- 1}}),

f_{bw} \approx \frac{β}{2 π} f_{ref} G,

where

K_{DCO}

is the gain of DCO,

K_{TDC}

is the gain of TDC, and

G_{loop} ((), Z)

is the loop gain.

N

is the division ratio,

α

and

β

are proportional and integral parameters of loop filter, respectively.…”

Section: Proposed Adpll Architecturementioning

confidence: 99%

“…Therefore, choosing optimized loop bandwidth is important. 13 To achieve the low jitter ADPLL design, the optimized loop bandwidth is required for specific output frequency.…”

Section: Adpll Designmentioning

confidence: 99%

“…The proposed VCO has periodic jitter of 0.2 ps and proposed 3-bit flash TDC have periodic jitter of 0.5 ps, respectively. The loop bandwidth of ADPLL extensively impacts the output jitter performance 13 of ADPLL. The relationship between loop bandwidth and gain is given by 13 F I G U R E 2 (A) Proposed ADPLL and (B) calibration process using LMS algorithm…”

Section: Proposed Adpll Architecturementioning

confidence: 99%

“…The loop bandwidth of ADPLL extensively impacts the output jitter performance 13 of ADPLL. The relationship between loop bandwidth and gain is given by 13 F I G U R E 2 (A) Proposed ADPLL and (B) calibration process using LMS algorithm…”

Section: Proposed Adpll Architecturementioning

confidence: 99%

See 3 more Smart Citations

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz.

show abstract

“…The loop bandwidth of ADPLL extensively impacts the output jitter performance 13 of ADPLL. The relationship between loop bandwidth and gain is given by 13

G_{loop} ((), Z) goodbreak= \frac{{NK}_{TDC} K_{DCO}}{1 - Z^{- 1}} * ((), α goodbreak+ \frac{β}{1 - Z^{- 1}}),

f_{bw} \approx \frac{β}{2 π} f_{ref} G,

where

K_{DCO}

is the gain of DCO,

K_{TDC}

is the gain of TDC, and

G_{loop} ((), Z)

is the loop gain.

N

is the division ratio,

α

and

β

are proportional and integral parameters of loop filter, respectively.…”

Section: Proposed Adpll Architecturementioning

confidence: 99%

“…Therefore, choosing optimized loop bandwidth is important. 13 To achieve the low jitter ADPLL design, the optimized loop bandwidth is required for specific output frequency.…”

Section: Adpll Designmentioning

confidence: 99%

Section: Proposed Adpll Architecturementioning

confidence: 99%

Section: Proposed Adpll Architecturementioning

confidence: 99%

See 2 more Smart Citations

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…This calls for the demand of the mixed-signal PLL [5], [6] design with the advantage of both analog PLL and digital PLL for a better jitter performance and environment noise immunity. For a given PLL structure, the optimal BW loop is essential to balance the in-band and out-of-band phase noise contributions and minimize the jitter [7], [8]. However, in the actual case, the reference frequency ( f REF ) limits the achievable BW loop .…”

Section: Introductionmentioning

confidence: 99%

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Qiu

Sun

Liu

et al. 2021

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

In this article, a mixed-signal, 32-kHz referencebased 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1× sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digitalto-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.

show abstract

A low-jitter leakage-free digitally calibrated phase locked loop

Kazeminia

Soltani²

2020

Computers & Electrical Engineering

View full text Add to dashboard Cite

A Background Calibration Technique to Control the Bandwidth of Digital PLLs

Cited by 15 publications

References 28 publications

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

A low-jitter leakage-free digitally calibrated phase locked loop

Contact Info

Product

Resources

About