A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC

Sakakibara, Masaki; Ogawa, Koji; Sakai, Shin-ichi; Tochigi, Yasuhisa; Honda, Katsuya; Kikuchi, Hidekazu; Wada, Takuya; Kamikubo, Yasunobu; Miura, Tsukasa; Nakamizo, Masahiko; Jyo, Naoki; Hayashibara, Ryo; Furukawa, Yohei; Miyata, Shinya; Yamamoto, Satoshi; Ota, Yoshiyuki; Takahashi, Hideki; Taura, Toshiharu; Oike, Yusuke; Tatani, Keiji; Nagano, Takashi; Ezaki, Takayuki; Hirayama, Teruo

doi:10.1109/isscc.2018.8310193

Cited by 55 publications

(20 citation statements)

References 2 publications

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“…The 3D stacking of a sensor layer and processing circuit layer allows us to attain efficient interconnections between the pixels and the columnparallel ADCs and also between the column-parallel ADCs and the processing circuits. Based on the 3D stacking, the major architecture of ADC may change from column parallel to pixel parallel in near future, and actually CISs with pixel-parallel ADCs with excellent performances have been reported [80]. In this paper, however, discussion is focused only on CISs using column-parallel ADCs.…”

Section: Technology Factors Relevant To the Evaluation Of Ciss And Comentioning

confidence: 99%

Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations

Kawahito

2018

IEICE Trans. Electron.

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This paper reviews architectures and topologies for column-parallel analog-to-digital converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of CISs using columnparallel ADCs based on figures-of-merit (FoM) with considering noise models which behave differently at low/middle and high pixel-rate regions. Various FoM considering different performance factors are defined. The defined FoM are applied to surveyed data on reported CISs using columnparallel ADCs which are categorized into 4 types; single slope, SAR, cyclic and delta-sigma ADCs. The FoM defined by (noise) 2 (power)/(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS' performance in all the pixel rates. Using the FoM defined by (noise) 2 (power)/(intrascene dynamic range)(pixel-rate), the effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified.

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Section: Technology Factors Relevant To the Evaluation Of Ciss And Comentioning

confidence: 99%

Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations

Kawahito

2018

IEICE Trans. Electron.

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“…The pixel-parallel CMOS image sensor has an escalating performance in providing a high frame rate with high-definition resolutions in video systems. This sensor has a signal processor for every pixel, used to process and store the pixel data, and provides a frame rate >10,000 frames/s [ 1 , 2 ]. Though the signal processors’ large footprint bounded the spatial resolution in pixel-parallel design, the 3D stacking architecture allows us to overcome this bottleneck by integrating pixel processors beneath each pixel [ 3 ].…”

Section: Introductionmentioning

confidence: 99%

HARP: Hierarchical Attention Oriented Region-Based Processing for High-Performance Computation in Vision Sensor

Bhowmik

Pantho

Bobda

2021

Sensors

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Cameras are widely adopted for high image quality with the rapid advancement of complementary metal-oxide-semiconductor (CMOS) image sensors while offloading vision applications’ computation to the cloud. It raises concern for time-critical applications such as autonomous driving, surveillance, and defense systems since moving pixels from the sensor’s focal plane are expensive. This paper presents a hardware architecture for smart cameras that understands the salient regions from an image frame and then performs high-level inference computation for sensor-level information creation instead of transporting raw pixels. A visual attention-oriented computational strategy helps to filter a significant amount of redundant spatiotemporal data collected at the focal plane. A computationally expensive learning model is then applied to the interesting regions of the image. The hierarchical processing in the pixels’ data path demonstrates a bottom-up architecture with massive parallelism and gives high throughput by exploiting the large bandwidth available at the image source. We prototype the model in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) for integrating with a pixel-parallel image sensor. The experiment results show that our approach achieves significant speedup while in certain conditions exhibits up to 45% more energy efficiency with the attention-oriented processing. Although there is an area overhead for inheriting attention-oriented processing, the achieved performance based on energy consumption, latency, and memory utilization overcomes that limitation.

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“…Massively parallel image acquisition in CMOS image sensors [ 1 , 2 , 3 , 4 , 5 ] is frequently based on time-to-digit analog-to-digital converters (ADCs) due to a relatively small silicon area and easy pixel integration. Time-mode ADCs are often used due to their advantages such as low noise (fixed pattern and temporal) and high dynamics.…”

Section: Introductionmentioning

confidence: 99%

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Kłosowski

Sun

2020

Sensors

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In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

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A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC

Cited by 55 publications

References 2 publications

Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations

Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations

HARP: Hierarchical Attention Oriented Region-Based Processing for High-Performance Computation in Vision Sensor

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

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