A 99 - 132 GHz Frequency Quadrupler with 8.5 dBm Peak Output Power and 8.8% DC-to-RF Efficiency in 130 nm BiCMOS

Wu, Kefei; Mansha, Muhammad Waleed; Hella, Mona M.

doi:10.1109/ims30576.2020.9223769

Cited by 14 publications

(3 citation statements)

References 15 publications

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“…The quadrupler presented in this paper delivers relatively the highest output power and widest bandwidth. Meanwhile, it achieves high gain without using supple- Table 2 summarizes the performance of the 130-220-GHz frequency quadrupler, and the results are compared with different state-of-the-art frequency quadruplers in paper [19][20][21][22][23][24][25][26][27]. The quadrupler presented in this paper delivers relatively the highest output power and widest bandwidth.…”

Section: Measurement Resultsmentioning

confidence: 99%

A 130-to-220-GHz Frequency Quadrupler with 80 dB Dynamic Range for 6G Communication in 0.13-μm SiGe Process

Cao

et al. 2022

Electronics

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This paper presents a broadband frequency quadrupler (FQ) implemented with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doublers (×2) operate at an input frequency of 32.5–55 GHz and 65–110 GHz, respectively. To properly drive the two doublers with enough input power and bandwidth, two transformer coupled power amplifiers (PAs) have been adopted. The former power amplifier is based on a neutralized capacitor structure and the latter is based on a transformer topology. A nonlinear device model and a systematic methodology to generate maximum power at second harmonic are proposed. By manipulating the device nonlinearity and optimizing the magnetically and capacitively coupled resonator (MCCR) matching networks, optimum conditions for harmonic power generation are provided. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and a high energy efficiency η of 3.7% at 210 GHz.

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Section: Measurement Resultsmentioning

confidence: 99%

A 130-to-220-GHz Frequency Quadrupler with 80 dB Dynamic Range for 6G Communication in 0.13-μm SiGe Process

Cao

et al. 2022

Electronics

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“…Table 2 compares the present D-band frequency multiplier with those reported for different transistor technologies [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43], [44], [45], [46], [47], [48], [49], [50], [51]. It can be seen that this work not only is the first D-band frequency multiplier based on the GaN HEMT technology, but also has the highest output power and the lowest fundamental leakage among all D-band frequency multipliers of any transistor technology.…”

Section: Discussionmentioning

confidence: 99%

A D-Band Frequency-Doubling Traveling-Wave Amplifier Through Monolithic Integration of a SiC SIW and GaN HEMTs

Li,

Fay,

Hwang

2024

IEEE J. Microw.

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We report a solid-state traveling-wave amplifier (TWA) realized through monolithic integration of transistors with a SiC substrate-integrated waveguide (SIW). The TWA uses a stepped-impedance microstrip line as the input divider, but a low-loss, high-power-capacity SIW as the output combiner. The input signal is distributed to four GaN high-electron mobility transistors (HEMTs) evenly in magnitude but with 90°successive phase delays at the fundamental frequency. The HEMTs are distributed in the SIW in a period of a half wavelength at the second harmonic frequency, so that their outputs are combined coherently at the SIW output. To overcome the limited speed of the HEMTs, they are driven nonlinearly to generate second harmonics, and their fundamental outputs are suppressed with the SIW acting as a high-pass filter. The measured characteristics of the TWA agree with that simulated at the small-signal level, but exceeds that simulated at the large-signal level. For example, under an input of 15 dBm at 70 GHz, the output at 140 GHz is 38-dB above that at 70 GHz. Under an input around 70 GHz and 20 dBm, the output around 140 GHz is 14 dBm with a 3-dB bandwidth of 6%. This is not only the first D-band frequency multiplier based on the GaN HEMT technology, but also one with the highest output power and the lowest fundamental leakage among all D-band multipliers of different transistor technologies. This proof-of-principle demonstration opens the path to improve the power, gain and efficiency of sub-terahertz TWAs with higher-performance transistors and drive circuits. Although the demonstration is through monolithic integration, the approach is applicable to heterogeneous integration with the SIW and transistors fabricated on separate chips.

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“…Frequency multiplication-based FM adopts either Npush [11]− [13] or the waveform shaping architecture [14], which creates harmonics of the input signal by using nonlinearities of the transistor. Then, the matching network extracts and delivers the desired harmonic to the load.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

et al. 2023

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This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (Gmax) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the Gmax at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237−263 GHz), respectively, while requiring a chip area of 0.071 mm 2 . Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.

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A 99 - 132 GHz Frequency Quadrupler with 8.5 dBm Peak Output Power and 8.8% DC-to-RF Efficiency in 130 nm BiCMOS

Cited by 14 publications

References 15 publications

A 130-to-220-GHz Frequency Quadrupler with 80 dB Dynamic Range for 6G Communication in 0.13-μm SiGe Process

A 130-to-220-GHz Frequency Quadrupler with 80 dB Dynamic Range for 6G Communication in 0.13-μm SiGe Process

A D-Band Frequency-Doubling Traveling-Wave Amplifier Through Monolithic Integration of a SiC SIW and GaN HEMTs

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

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