A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications

Fujii, Hiroki; Tokumitsu, Shigeo; Mori, Toshiyuki; Yamashita, T.; Maruyama, T.; Maruyama, Yoshiki; Nishimoto, S; Arie, Hiroyuki; Kubo, S.; Ippóshi, T.

doi:10.23919/ispsd.2017.7988896

Cited by 10 publications

(2 citation statements)

References 4 publications

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“…The floating gate effect can be eliminated by contacting the DTI to the substrate creating a connection to ground. The process flow for creating a substrate contact follows the typical flow, but after the silicon dioxide liner growth, a self-aligned isotropic etch is performed to remove the liner at the bottom, and then the trench is filled with either doped polysilicon or tungsten (Figure 1) 6 . Due to the self-aligned etch process, the initial trench etch determines the final sidewall profile of the trench (see Figure 2) and the bottom width (the width of the trench prior the the bottom rounding) becomes critical because it will determine the contact resistance of the DTI.…”

Section: Introductionmentioning

confidence: 99%

Non-destructive measurement of bottom width in deep trench isolation structures using IRCD metrology

Keller,

Poulingue,

Grynko

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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As scaling in semiconductor devices continues, the aspect ratios of deep trench isolation (DTI) structures have increased. DTI structures are used in power devices, power management ICs and image sensors as a method to isolate active devices by reducing crosstalk, parasitic capacitance, latch-up and allowing for an increase breakdown voltage of active devices. Measurement of these structures in high volume manufacturing (HVM), with non-destructive technology, has mostly been limited to the depth and top width of the DTI structure, while the bottom width (BCD) has not been able to be reliably measured. Here we present two different optical metrologies, "conventional" OCD and IRCD, that operate in the UV-VIS-NIR and MIR region of the electromagnetic spectrum, respectively, and discuss the measurability of DTI sidewall profile, bottom width, and depth in BCD (Bipolar CMOS DMOS) power management IC devices for each method at various pitches and line to space ratios. Experimental data will be presented showing sensitivity and discrimination of IRCD to a DOE specifically on the bottom width for three different structures.

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Section: Introductionmentioning

confidence: 99%

Non-destructive measurement of bottom width in deep trench isolation structures using IRCD metrology

Keller,

Poulingue,

Grynko

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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“…With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (R on,sp ) and maximizing off-state breakdown voltage (BV) [1][2][3][4][5][6][7][8][9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of R on,sp vs. BV for LDMOS devices [10][11][12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

et al. 2019

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An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.

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BCD Process Technologies

Croce

Andreini²,

Galbiati³

et al. 2022

Springer Handbook of Semiconductor Devices

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A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications

Cited by 10 publications

References 4 publications

Non-destructive measurement of bottom width in deep trench isolation structures using IRCD metrology

Non-destructive measurement of bottom width in deep trench isolation structures using IRCD metrology

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

BCD Process Technologies

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