A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput

Yoo

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

2011

Phase-change RAM (PRAM) is considered to be a promising candidate to complement or replace DRAM which is expected to suffer from device scaling in near future. PRAM has the advantages of better scaling and non-volatility. However, PRAM suffers from write endurance and long latency. Diff erential write, where only modified bits are updated in memory, is required to reduce bit updates in PRAM to improve both write endurance and latency. Due to the constraint of peak write current in PRAM, write unit size is typically smaller than the row buffer size (the unit of precharge operation in conventional DRAM). Thus, write latency becomes a function of the amount of modified data bits. Read latency, which is more critical in system performance than write latency, is affected by such long and variable write latency in PRAM. In our work, we investigate a method of memory access scheduling for PRAM which applies write cancellation while taking into account variable write latency in diff erential writes in order to funher improve read latency. Given the information of write latency, the proposed idea offers average 26% further improvement in PRAM read latency. IntroductionPhase-Change RAM (PRAM) is expected to be utilized in several areas, e.g., non-volatile storage and main memory (as a part together with DRAM [1] [2] or as the sole component in main memory [3]). PRAM gives benefits such as non-volatility and better scaling than DRAM. However, its limitations of write endurance, write power, and read/write latency can prevent its widespread usage. Especially, write latency is 3-4 times larger than read latency and about 10 times larger than DRAM read/write latency. Improving write-related performance is one of the most important problems in PRAM since read performance, which typically determines system performance, can be significantly affected by write performance. For instance, if a critical read request (e.g., cache miss) to a PRAM bank needs to wait for a preceding long latency write request (to the same bank) to be finished, then the read request will suffer from a large latency thereby incurring a significant degradation in system performance.Existing solutions to resolve the problem of write-related performance degradation in PRAM can be classified into two groups: one for adopting write buffer and the other for reducing the amount of write data. The write buffer, typically DRAM buffer in the hybrid DRAM and PRAM memory subsystem [1][4] allows subsequent reads to bypass preceding writes thereby mitigating write-related performance degradation. However, this solution has two drawbacks: write buffer cost and forced writes. Especially, if the write buffer becomes full, the write data need to be flushed to the PRAM, which is called forced writes. During the execution of forced writes, read requests cannot be served thereby hurting read performance.The other solution to write-related performance degradation is to reduce the amount of write data. In [1][3], dirty information is utilized to store only the modified portion (e...

Section: Preliminarymentioning

confidence: 99%

Section: Our Motivationmentioning

confidence: 99%

Reducing read latency in phase-change RAM-based main memory

Yoo

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

2011

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

“…embedded Flash, eFlash, [5]- [6]) are unable to achieve low-VDD operations due to: (1) charge-pumped circuits (CP) at a low VDD generating voltage/current that is insufficient to meet high-voltage highpower write requirements, and (2) a lack of a robust lowvoltage read scheme. More recent forms of memory, such as STT-MRAM [7]- [8], phase-change memory (PRAM) [9]- [11], and resistive RAM (ReRAM) [12]- [14], have achieved lower write power and faster write speeds than eFlash. However, STT-MRAM has a small resistance-ratio (R-ratio) between states, resulting in read difficulty at low VDD and PRAM consumes large write current, which prevents the application of low VDD to charge pump circuits.…”

mentioning

confidence: 99%

A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips

Chang

Hung

et al. 2014

Many mobile chips with low supply voltage (VDD) require low-voltage embedded nonvolatile memory (eNVM) to enable low-power read operations and zero-standby-current power-off storage. ReRAM has a lower write-voltage (V W ), smaller write-current (I W ), and larger resistance-ratio than other NVMs, making it a good candidate for low-VDD eNVM, as long as the following two challenges can be overcome: (1) the failure of level-shifters (LSs) to operate with a low input voltage (VDDL) during write operations, particularly under high converting voltages (VDDH); (2) the consumption of large DC current by LS resulting in degradation in VDDmin for the on-chip chargepump, particularly in NVMs with a large number of rows. This study proposes a pseudo-diode-mirrored (PDM) LS to achieve low VDDL, while maintaining a small DC current. PDM LSs were fabricated in a 65nm 4Mb embedded ReRAM macro, which achieved 0.1V minimum-VDDL at VDDH=2V.

Emerging Memory Technologies

“…Unfortunately, it suffers from serious process variation issues [1]. Another alternative technology is the embedded phase change memory (PCM) [5], a new nonvolatile memory that can achieve very high density. However, its slow access speed makes PCM unsuitable as a replacement for SRAM.…”

mentioning

confidence: 99%

STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices

Sun

et al. 2013

Spin-transfer torque random access memory (STT-RAM) is a promising new nonvolatile technology that has good scalability, zero standby power, and radiation hardness. The use of STT-RAM in last level on-chip caches has been proposed as it significantly reduced cache leakage power as technology scales down. Having a cell area only 1/9 to 1/3 that of SRAM, this will allow for a much larger cache with the same die footprint. This will significantly improve overall system performance, especially in this multicore era where locality is crucial. However, deploying STT-RAM technology in L1 caches is challenging because write operations on STT-RAM are slow and power-consuming. In this chapter, we propose a range of cache hierarchy designs implemented entirely using STT-RAM that delivers optimal power saving and performance. In particular, our designs use STT-RAM cells with various data retention times and write performances, made possible by novel magnetic tunneling junction (MTJ) designs. For L1 caches where speed is of the utmost importance, we propose a scheme that uses fast STT-RAM cells with reduced data retention time coupled with a dynamic refresh scheme. We will show that such a cache can achieve 9.2 % in performance improvement and saves up to 30 % of the total energy when compared to one that uses traditional SRAM. For lower-level caches with relatively larger cache capacities, we propose a design that has partitions of different retention characteristics and a data migration scheme that moves data between these partitions. The experiments show that on the average, our proposed multiretention-level STT-RAM cache reduces total energy by as much as 30-70 % compared to previous single retention-level STT-RAM cache, while improving IPC performance for both 2-level and 3-level cache hierarchies. IntroductionIncreasing capacity and cell leakage have caused the standby power of SRAM on-chip caches to dominate the overall power consumption of the latest microprocessors. Many circuit design and architectural solutions, such as V DD scaling [14], power gating [17], and body biasing [13], have been proposed to reduce the standby power of caches. However, these techniques are becoming less effective as technology scaling has caused the transistor's leakage current to increase exponentially. Researchers have been prompted to look into the alternatives of SRAM technology. One possibility is the embedded DRAM (eDRAM) which is denser than SRAM. Unfortunately, it suffers from serious process variation issues [1]. Another alternative technology is the embedded phase change memory (PCM) [5], a new nonvolatile memory that can achieve very high density. However, its slow access speed makes PCM unsuitable as a replacement for SRAM.Another substitute for SRAM, the spin-transfer torque RAM (STT-RAM), is receiving significant attention because it offers almost all the desirable features of a universal memory: the fast (read) access speed of SRAM, the high integration density of DRAM, and the nonvolatility of Flash memory. Also, ...