Reducing read latency in phase-change RAM-based main memory

Abstract

Phase-change RAM (PRAM) is considered to be a promising candidate to complement or replace DRAM which is expected to suffer from device scaling in near future. PRAM has the advantages of better scaling and non-volatility. However, PRAM suffers from write endurance and long latency. Diff erential write, where only modified bits are updated in memory, is required to reduce bit updates in PRAM to improve both write endurance and latency. Due to the constraint of peak write current in PRAM, write unit size is typically smaller than the row buffer size (the unit of precharge operation in conventional DRAM). Thus, write latency becomes a function of the amount of modified data bits. Read latency, which is more critical in system performance than write latency, is affected by such long and variable write latency in PRAM. In our work, we investigate a method of memory access scheduling for PRAM which applies write cancellation while taking into account variable write latency in diff erential writes in order to funher improve read latency. Given the information of write latency, the proposed idea offers average 26% further improvement in PRAM read latency. IntroductionPhase-Change RAM (PRAM) is expected to be utilized in several areas, e.g., non-volatile storage and main memory (as a part together with DRAM [1] [2] or as the sole component in main memory [3]). PRAM gives benefits such as non-volatility and better scaling than DRAM. However, its limitations of write endurance, write power, and read/write latency can prevent its widespread usage. Especially, write latency is 3-4 times larger than read latency and about 10 times larger than DRAM read/write latency. Improving write-related performance is one of the most important problems in PRAM since read performance, which typically determines system performance, can be significantly affected by write performance. For instance, if a critical read request (e.g., cache miss) to a PRAM bank needs to wait for a preceding long latency write request (to the same bank) to be finished, then the read request will suffer from a large latency thereby incurring a significant degradation in system performance.Existing solutions to resolve the problem of write-related performance degradation in PRAM can be classified into two groups: one for adopting write buffer and the other for reducing the amount of write data. The write buffer, typically DRAM buffer in the hybrid DRAM and PRAM memory subsystem [1][4] allows subsequent reads to bypass preceding writes thereby mitigating write-related performance degradation. However, this solution has two drawbacks: write buffer cost and forced writes. Especially, if the write buffer becomes full, the write data need to be flushed to the PRAM, which is called forced writes. During the execution of forced writes, read requests cannot be served thereby hurting read performance.The other solution to write-related performance degradation is to reduce the amount of write data. In [1][3], dirty information is utilized to store only the modified portion (e...