A 90-nm Radiation Hardened Clock Spine

Chellappa, Srivatsan; Clark, Lawrence T.; Holbert, Keith E.

doi:10.1109/tns.2012.2183647

Cited by 13 publications

(6 citation statements)

References 18 publications

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“…Each lists contains 60 flip-flops (the most critical 5 %) and the same 42 flip-flops can be found in each list, which results in an overlap of 70 %. In contrary, when comparing the most vulnerable flip-flops related to SETs in (1) wishbone_if0.cpureg_config0(0) tx_hold_fifo0.fifo0.ctrl0.rd_ptr(2) tx_hold_fifo0.fifo0.ctrl0.rd_ptr(1) tx_data_fifo0.fifo0.ctrl0.rd_ptr(0) tx_data_fifo0.fifo0.ctrl0.rd_ptr (1) tx_dq0.curr_state_pad(0) tx_data_fifo0.fifo0.ctrl0.rd_ptr (5) tx_data_fifo0.fifo0.ctrl0.rd_ptr(3) tx_data_fifo0.fifo0.ctrl0.rd_ptr (6) tx_dq0.txhfifo_wen tx_dq0.byte_cnt(6) tx_hold_fifo0.fifo0.ctrl0.wr_ptr (3) tx_dq0.crc32_d8 (9) tx_dq0.crc32_d8(25) tx_dq0.crc32_d8(28) tx_hold_fifo0.fifo0.ctrl0.wr_ptr (2) tx_dq0.crc32_d8 (16) tx_dq0.crc32_d8(29) tx_dq0.crc32_d8(24) tx_dq0.crc32_d8(26) tx_dq0.crc32_d8 (7) tx_dq0.crc32_d8 (6) tx_dq0.crc32_d8 (17) tx_dq0.crc32_d8 (3) tx_dq0.crc32_d8 (5) tx_dq0.crc32_d8(4) tx_dq0.crc32_d8 (8) tx_dq0.crc32_d8 (27) Functional Failure Rate . This is particularly important when selective hardening of the sequential logic is considered.…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…This information can provide guidelines to the circuit designer to improve robustness of the clock distribution network. For example, techniques for selectively harden the most critical clock buffers are shown in [6] and [16]. Further, the ∆-TMR technique can be used which hardens the sequential logic against SEUs, but also introduces delays into the data path in such a way the logic is protected against SETs in the clock signal [17].…”

Section: Fault Injection Simulation Campaignmentioning

confidence: 99%

“…However, due to technology scaling, lower supply voltages and higher operating frequencies, other circuit features such as the clock distribution network (CDN), reset circuitry, etc. become also more vulnerable to transient faults [3]- [6] and could cause circuitwide effects that are more difficult to mitigate and to correct. Indeed, clock buffers from the clock distribution networks have a high fan-out and very few masking mechanism; Single-Event Transients occurring in these cells can potentially reach many sequential cells and state elements and thus, significantly contribute to the overall functional failure rate.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Lange

Glorieux

Alexandrescu

et al. 2019

2019 14th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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With technology scaling, lower supply voltages, and higher operating frequencies clock distribution networks become more and more vulnerable to transients faults. These faults can cause circuit-wide effects and thus, significantly contribute to the functional failure rate of the circuit. This paper proposes a methodology to analyse how the functional behaviour is affected by Single-Event Transients in the clock distribution network. The approach is based on logic-level simulation and thus, only uses the register-transfer level description of a design. Therefore, a fault model is proposed which implements the main effects due to radiation-induced transients in the clock network. This fault model enables the computation of the functional failure rate caused by Single-Event Transients for each individual clock buffer, as well as the complete network. Further, it allows the identification of the most vulnerable flip-flops related to Single-Event Transients in the clock network.The proposed methodology is applied in a practical example and a fault injection campaign is performed. In order to evaluate the impact of Single-Event Transients in clock distribution networks, the obtained functional failure rate is compared to the error rate caused by Single-Event Upsets in the sequential logic.

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Section: Comparison and Discussionmentioning

confidence: 99%

Section: Fault Injection Simulation Campaignmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Lange

Glorieux

Alexandrescu

et al. 2019

2019 14th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

View full text Add to dashboard Cite

show abstract

“…The Radiation Hardening by Design (RHBD) approaches mitigated the soft error vulnerabilities effectively. Chellappa et al [1] described the RHBD Clock Distribution Network (CDN) that synchronized the signals by using the Integrated Circuits (IC) in the presence of Single Event Transistors (SET). The RHBD utilized the techniques to reduce the jitter and detected the error due to SET.…”

Section: Related Workmentioning

confidence: 99%

“…The utilization of minimal width transistors with the constant ion deposited charges makes the circuit as vulnerable to soft errors called Single Event Effects (SEE) [1]. The entire circuits of IC are controlled by Clock Distribution Network (CDN) and hence the hardening process is difficult.…”

Section: Introductionmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

Hao

Chen

Huang

et al. 2017

Sci. China Inf. Sci.

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A 90-nm Radiation Hardened Clock Spine

Cited by 13 publications

References 18 publications

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

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