A 9-ns 1-Mbit CMOS SRAM

Sasaki, K.; Hanamura, S.; Ueda, Kazuhiro; Oono, T.; Minato, O.; Sakai, Yoshio; Meguro, S.; Tsunematsu, M.; Masuhara, T.; Kubotera, M.; Toyoshima, Hideo

doi:10.1109/jssc.1989.572583

Cited by 41 publications

(6 citation statements)

References 8 publications

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“…The read function of the WDSRAM is supported with the horizontal abutment of the pmos cross coupled amplifier [4] MCAMPCCA_FDSEC [1]. This cell is also included in the Ceid Memory Library [1] and is presented in its schematic and layout views at Fig 7 (c) and (d) respectively.…”

Section: E the Sector Memory Read -Write Blocksmentioning

confidence: 99%

Implementation of a 256x8 Sector Size SRAM grid with memory write speedup on CeidMem library

Simopoulos

Haniotakis²,

Alexiou

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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In this work, the implementation of a static memory grid, consisting of sectors with size 256x8 bits, is presented. The grid supports memory write speedup leading to a minimized write pulse of at least 5 times than the typical implementation of static memories. All implementations have been done using the CeidMem Static Memory Library and the simulation results of the behavior of the grid is presented and analyzed.

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Section: E the Sector Memory Read -Write Blocksmentioning

confidence: 99%

Implementation of a 256x8 Sector Size SRAM grid with memory write speedup on CeidMem library

Simopoulos

Haniotakis²,

Alexiou

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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“…Architectural Solutions: Dual modular redundancy schemes are used in many designs for providing memory structure reliability, but they are highly inefficient in terms of the overhead [5], [34]. A popular architectural solution is to use redundant rows and/or columns [24].…”

Section: Related Workmentioning

confidence: 99%

Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines

Ansari

Gupta

Feng

et al. 2011

IEEE Trans. Comput.

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Abstract-Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-chip caches, it is important to protect these SRAM structures against lifetime and manufacture-time failures. Designers typically over-provision caches with additional resources to overcome hard-faults. However, static allocation and binding of redundant spares results in low utilization of the extra resources and ultimately limits the number of defects that can be tolerated. This work re-examines the design of process variation tolerant on-chip caches with a focus on providing the flexibility and dynamic reconfigurability necessary to tolerate large numbers of defects with modest hardware overhead. Our approach, ZerehCache, virtually reorganizes the cache data array using a permutation network to provide more degrees of freedom for spare allocation. A graph coloring algorithm is used to configure the network and identify the proper mapping of replacement elements. We perform an extensive design space exploration of both L1/L2 caches to identify several Pareto optimal ZerehCaches. Given this optimal design points, we employ ZerehCache to extend the effective lifetime of the on-chip caches and prevent early lifetime failures. Finally, yield analysis studies, performed on a population of 1000 chips at the 45nm technology node demonstrated that an L1 design with 16% and an L2 designs with 8% area overheads achieve yields of 99% and 96%, respectively.

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“…Some commonly used CMOS SRAM sense amplifiers: static gates (a), domino gates (b), the current mirror static amplifier (c), differential regenerative (d) and ''DEC'' differential regenerative sense amplifier (e). [6][7][8][9][10][11]. The BL differential voltage swing developed across the sense amplifier input must be larger than the sense amplifier offset voltage (due to its internal transistor and BL induced mismatches).…”

Section: Sram Sensingmentioning

confidence: 99%

“…The speed of the read path becomes the overriding concern. This sense amplifier is considerably slower than other circuits [6]. Additionally, it has severe common mode rejection ratio issues [7], which are exacerbated by the commonly used PMOS BL pre-charge to V DD in modern SRAM designs.…”

Section: Sram Sensingmentioning

confidence: 99%