A 9-bit current-steering Digital to Analog Converter for differential dc-offset compensation of a baseband chain

Abstract

A current-steering Digital to Analog Converter (IDAC) to compensate dc-offset of a baseband chain in a Synthetic Aperture Radar (SAR) receiver is presented in this paper. The differential dc-offset can be injected with the current steer controlled by 9 digital control bits. The simulated LSB is 1.4 mV and the differential voltage range is 283 mV when it is connected to the baseband chain. This IDAC is implemented in a 130 nm CMOS technology and occupies 0.05 mm 2 of silicon area. From the postlayout simulation of the IDAC, the voltage range satisfies the specification obtained from the Monte Carlo simulations of the baseband chain. The 1 Least Significant Bit (1LSB) of the IDAC ensure the dc-offset at the input of the following ADC met the system requirement.

High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

“…Therefore, the least significant bit (LSB) of the DAC should be less than the minimum DC offset of the mixers and LPF, while the total current of the DAC should be larger than the maximum DC offset of the mixers and the LPF [30]. According to the equivalent input DC offset voltage of the OPAMP through Monte Carlo simulation [33] and the gain of the mixers and LPF shown in Table 1, the DAC employed in the DCOC circuits is shown in Figure 11. This was an 8-bit, full-thermometer, current-steering DAC with an LSB current of 120 nA, which could ensure that the output DC offset of the mixer and low-pass filter could be limited to less than -50 dBFS (differential of 1.4 mV, ADC full swing of 6.5 dBm) after calibration in the analog domain.…”

An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers

“…In order to obtain the full scale of the DAC, the input equivalent DC offset of the OPAMP is simulated using Monte Carlo simulation. The results (including temperature variation: À40{80°C) are shown in Table II [31]. To meet the system requirements like noise, power consumption, and linearity, the detailed parameters of the receiver are given in Table III. Combined with the above conditions, an 8-bit currentsteering DAC which is adopted in both Mixer and LPF stage is shown in Fig.…”