A 8bit two stage time-to-digital converter using time difference amplifier

Mandai, Shingo; Nakura, Toru; Ikeda, Makoto; Asada, Kunihiro

doi:10.1587/elex.7.943

Cited by 2 publications

(2 citation statements)

References 9 publications

(10 reference statements)

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“…Although the coarse-fine conversion architectures based on a time residue amplification [4,27,28] have realized ∼1 ps time resolution, these techniques often suffer from a large chip area and a high power consumption. Concepts of pipeline [29,30], SAR [31], cyclic [32], two-step [11,38,39].…”

Section: Time-to-digital Convertersmentioning

confidence: 99%

Time-domain approach for analog circuits in deep sub-micron LSI

Asada

Nakura²,

Iizuka

et al. 2018

IEICE Electron. Express

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As the scaling of LSI is going to extremely fine regions toward the ultimate feature size, one of difficulties faced in analog circuit design is reduction of the dynamic range (DR) due to the supply voltage reduction. Unlike digital circuits, where the noise margin for logic operation is the key criterion, analog circuits need an enough DR. The reduced supply voltage directly results in DR degradation of the conventional analog circuits in the voltage-domain. Especially in mixed-signal LSIs, supply voltage instability, caused by logic operation, tends to degrade DR further. In this paper, we will first discuss potential capability of a new paradigm of time-domain circuits by comparing with the conventional voltage/current-domain circuits in terms of DR and power consumption. Next, as basic circuit components for the time-domain approach, current status of TDA (Time-Difference Amplifier) and TDC (Time-to-Digital Converter) will be reviewed. Finally, some application examples of the time-domain circuits are introduced to demonstrate the feasibility of the time-domain approach.

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Section: Time-to-digital Convertersmentioning

confidence: 99%

Time-domain approach for analog circuits in deep sub-micron LSI

Asada

Nakura²,

Iizuka

et al. 2018

IEICE Electron. Express

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“…TDCs based on a Vernier delay line (VDL) [2] and time amplifiers (TAs) [3,4] are usually used to achieve sub-gate resolution. However, limited TDC resolution still causes quantization errors using both of the methods described above.…”

Section: Introductionmentioning

confidence: 99%

A MASH 1-1-1 ΔΣ time-to-digital converter based on two-stage time quantization

Wang

Chen

et al. 2013

IEICE Electron. Express

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A MASH 1-1-1 ΔΣ time-to-digital converter (TDC), based on two-stage time quantization, was designed with a 0.13 μm CMOS process and a 1.2 V supply. A classical delay line and a Vernier delay line were used for coarse and fine quantization, respectively. Third-order noise-shaping was achieved using the proposed MASH 1-1-1 ΔΣ modulator. Simulation results showed that a resolution of up to 5.5 ps and a measurement range of 38.4 ns could be achieved. The proposed TDC consumes 4.9 mW and occupies 0.28 mm 2 .

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A 8bit two stage time-to-digital converter using time difference amplifier

Cited by 2 publications

References 9 publications

Time-domain approach for analog circuits in deep sub-micron LSI

Time-domain approach for analog circuits in deep sub-micron LSI

A MASH 1-1-1 ΔΣ time-to-digital converter based on two-stage time quantization

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