A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme

Makigawa, K.; Ono, Koichi; Ohkawa, Takenao; Matsuura, K.; Segami, M.

doi:10.1109/vlsic.2006.1705348

Cited by 26 publications

(13 citation statements)

References 3 publications

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“…Through this work, the symmetry of zero-crossing composition can be improved. However, it causes some problems of a complicated encoding process and a lot of switching arrays [10]. In order to solve that problem, the proposed ADC applies a novel digital encoder.…”

Section: Architecturementioning

confidence: 99%

“…Thus it is a great constraint of high resolution ADCs because of its huge power consumption and chip area. To overcome those problems, folding structure has been continuously studied [4][5][6][7][8][9][10][11][12][13][14][15][16]. However, folding ADCs have an asymmetry error at the boundary conditions, since there is even number of folding blocks [5].…”

Section: Introductionmentioning

confidence: 99%

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A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Lee¹,

Lee²,

Song

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99 mm 2 and the power dissipation is about 120 mW.The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

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Section: Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Lee¹,

Lee²,

Song

2014

JSTS:Journal of Semiconductor Technology and Science

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“…Folding and Interpolating ADCs (Makigawa et al, 2006) consist of a relatively small number of comparators. Different groups of reference values are applied to these comparators within a sampling period.…”

Section: Other Common Adc Architecturesmentioning

confidence: 99%

Asynchronous Analogue-to-Digital Conversion Techniques

Petrellis¹,

Birbas²,

Kikidis³

et al. 2010

Factory Automation

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“…Folding and interpolating are both methods of reducing the power consumption in the flash-type ADCs [5,6,7,8,9,10,11]. The folding architecture reduces the number of comparators and the interpolating architecture reduces the number of pre-amplifiers.…”

Section: Introductionmentioning

confidence: 99%

“…For example, a cascaded folding architecture is proposed to improve the bandwidth [12]. A power-efficient averaging method is proposed to improve mismatches among folders or interpolators [8,9]. A pipelined folding interpolating architecture is proposed to reach higher sampling rate [7,10].…”

Section: Introductionmentioning

confidence: 99%

A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>

Wang¹,

Ye³

et al. 2014

IEICE Electron. Express

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This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAI-ADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficiency of speed. The ADC implemented in 0.13-µm CMOS technology achieves the signal-to-noise-and-distortion ratio (SNDR) of 37.89 dB and the spurious-free dynamic range (SFDR) of 45.89 dB for 498 MHz input frequency at the rate of 1.0 GS/s. The power consumption is 98 mW with sampling rate of 1.0 GS/s and supply voltage of 1.2/ 2.5 V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step.

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A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme

Cited by 26 publications

References 3 publications

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Asynchronous Analogue-to-Digital Conversion Techniques

A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>

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