A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…Alternatively, the opening of data eyes can be used to guide DFE search [71,72]. Eye-opening can be captured using an Eye-Opening Monitor (EOM) [73][74][75][76][77][78][79][80][81]. Jitter-based eye-opening monitors that minimize timing jitter at the edges of data eyes also emerged [82].…”

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

“…Table 4 shows performance comparisons with related works. Synchronous links [7], [8] need a synchronizer if they are used in the asynchronous multi-chip NoCs. The delay overhead due to the synchronizer is not easily estimated for performance comparisons as the delay time is varied depending on the asynchronous data-transmission condition in the NoCs.…”

“…Some synchronous inter-chip link proposals achieve more than 10 Gbps/link [7], [8]. The throughput is high, but requires synchronizers between the synchronous links and asynchronous computation blocks in the asynchronous multi-chip NoCs.…”

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

“…In the case of the M-DFE (Fig. 8), entries of LUT0, are calculated by (9) where is a binary number representing possible combinations of the slicer outputs that has a following relationship with an integer, : (10) The entries of other LUTs are calculated in a similar way. Although this LUT entry calculation is not implemented on-chip, this operation can be hard-wired via low-power adder trees because the throughput requirement of this operation is as low as several MHz (in IFS length).…”