A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering

A 41 μW real-time adaptive neural spike classifier

“…The output is fed to a back-end signal processing unit, which provides additional filtering and executes a spike sorting. Several previous spike-sorting DSP realizations [4]- [6] have implemented spike detection and feature extraction, however, most spike sorting clustering algorithms, e.g., means, and superparamagnetic clustering, are offline, unsupervised algorithms not usable for real-time data streams.…”

“…In contrast, the compiled SRAM has limited read noise margin, and consequently, cannot be scaled below 0.7V. The register-bank memories are organized as spike registers [4], as shown in Figure 2b). Each spike register module consists of 10-bit registers to save the spike waveforms, and a delay line for clock gating.…”

A 2.7μW/MIPS, 0.88GOPS/mm2 distributed processor for implantable brain machine interfaces

“…The other is associated with accelerating adaptive filters that map these spike trains to estimate cognitive dynamics or invoked limb movement. Typical examples for acquiring neural activity are fully synthesized cores [4] [5] that have been successful in realizing implantable solutions. In contrast high level decoding is predominantly performed by FPGAs as integration makes less sense at the system level [6].…”

Live demonstration: A scalable 32-channel neural recording and real-time FPGA based spike sorting system

“…Previous published approaches for neural spike-sorting have therefore demonstrated that (up to 64 channels) can be processed using custom ASIC designs, novel clustering algorithms and a variety of techniques to efficiently use resources [8], [9]. However, a novel 2 stage hybrid approach leveraging all the performance of standard algorithms was described in [2] and is implemented here in low power commercial off the shelf hardware.…”