A 71dB dynamic range third-order &amp;#x0394;&amp;#x03A3; TDC using charge-pump

Gande, Manideep; Maghari, Nima; Oh, Tae-Hwan; Moon, Un-Ku

doi:10.1109/vlsic.2012.6243843

Cited by 21 publications

(17 citation statements)

References 5 publications

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“…The method of using a charge pump has been presented to convert time information into voltage [10]. Since the charge pump only works as a time-to-voltage converter, it is unable to implement the highorder loop filter without the following voltage integrators.…”

Section: A Proposed Half-delay Time Integratormentioning

confidence: 99%

“…The output time signal T OUT is generated using the comparator and a ramp signal, V RAMP . Compared with [10], the proposed time integrator has the advantage that the high-order loop filter can be easily achieved by cascading the proposed time integrator, since two inputs and an output are synchronous time-domain signals. Fig.…”

Section: A Proposed Half-delay Time Integratormentioning

confidence: 99%

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A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator

Kwon

Kim

2016

IEEE Trans. VLSI Syst.

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A compact, low-power, single-loop third-order delta-sigma ( ) time-to-digital converter (TDC) for time-mode signal processing is presented in this brief. In general, a high-resolution TDC requires a cascadable time integrator to increase the order of the loop filter. However, implementing the time integrator has been very challenging owing to the difficulty in storing time information. In this brief, we present a low-power half-delay time integrator, which is simply composed of two AND gates, a charge pump, and a comparator. The proposed time integrator can be easily cascaded (serially connected) to implement a loop filter with high-order noise shaping. The prototype TDC fabricated in 0.11-μm CMOS process occupies an active area of 0.11 mm 2 , consuming 0.4 mW from a 1.2 V supply. It achieves the dynamic range of 81 dB over a signal bandwidth of 50 kHz, and the resolution of 4.7 ps over a measurable range of 39.06 ns, which is half the clock period.Index Terms-Delta-sigma ( ) modulator, high resolution, low power, time-to-digital converter (TDC). 1063-8210

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Section: A Proposed Half-delay Time Integratormentioning

confidence: 99%

Section: A Proposed Half-delay Time Integratormentioning

confidence: 99%

A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator

Kwon

Kim

2016

IEEE Trans. VLSI Syst.

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“…A group of regenerative latches and dynamic DFF make up the ZCD sampler, they are enabled/sampled by the adjacent two clock edges, and their output is ANDed in groups of two to flag the zero-crossing event, which is always captured by the second reference clock edge after zerocrossing. This particular ZCD sampler architecture is beneficial in mitigating the metastability effect when zerocrossing event is too close to clock edges [15]. The 16-input NOR gate gathers the output from LATCH/DFF bank to produce the PWM of quantizer output V PWM .…”

Section: B the Circuit Realization Of Time-interleaved Quantizermentioning

confidence: 99%

A Continuous-Time <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma$</tex-math></inline-formula> ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation

Venkatram

Maghari

et al. 2015

IEEE Trans. Circuits Syst. II

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This paper presents a 120MS/s continuous-time ∆Σ ADC with a dual-slope-based time-interleaved quantizer in a 0.18µm CMOS process. Excess loop delay of two sample clocks is compensated using the time information made available through interleaved channel coupling. As a result, one full clock cycle is afforded to DAC DEM operation, allowing for a digitally synthesized DEM block.Index Terms-Analog-to-digital conversion (ADC), CMOS analog integrated circuits, delta-sigma modulation, excess loop delay compensation. I.1549-7747 (c)

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“…The prototype IC implemented in 0.18µm process demonstrated 78dB SNDR in 1MHz bandwidth with 1.35mW analog and 1.55mW digital power consumption. This idea has spawned couple other interesting implementations, including a two-step residue discharging quantizer [34] and pulse-width modulated feedback time-to-digital converter [35]. The use of time-based and/or phase-based quantization is expected to be more efficient and desirable in scaled CMOS processes due to reduced voltage headroom and increased time resolution (due to faster time transition).…”

Section: Noise Shaped Integrating Quantizermentioning

confidence: 99%

Emerging analog-to-digital converters

Maghari

Moon

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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Many analog IC designers and students are naturally drawn to ADCs. While some ADC realizations have had a lasting impact including pipelined ADCs with digital redundancy, flash ADCs with folding and interpolation, and multi-bit deltasigma modulators with dynamic element matching, there are many more recent and emerging ADC design techniques that are receiving much attention and also gaining momentum in some areas. Many of these ideas are showered with doubts and honest criticism. However, we may also be entering a new era where a few of these developments could help resolve the tough submicron scaling challenge that analog designers face today. This paper will summarize and ponder the impact of a few selective as well as random slices of these emerging ADC designs.

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A 71dB dynamic range third-order ΔΣ TDC using charge-pump

Cited by 21 publications

References 5 publications

A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator

A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator

A Continuous-Time <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma$</tex-math></inline-formula> ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation

Emerging analog-to-digital converters

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