A 70V UMOS Technology with Trenched LOCOS Process to Reduce C<sub>gs</sub>

Hao, Wang; Trescases, Olivier; Xu, H.P.E.; Ng, Wai Tung; Fukumoto, K.; Ishikawa, Akira; Furukawa, Y.; Imai, H.; Naito, Takashi; Satô, Norio; Sakai, Kenichi; Tamura, Shigehiko; Takasuka, K.

doi:10.1109/ispsd.2007.4294962

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“…2. The LOCOS UMOS achieved a breakdown voltage of 73 V and R on,sp = 85 mΩ · mm 2 at V gs = 3.5 V. The on-resistance reduced to R on,sp = 60 mΩ · mm 2 at V gs = 10 V [5].…”

Section: Resultsmentioning

confidence: 94%

Observation and Utilization of Boron Segregation in Trench MOSFETs to Improve Figure of Merit (FOM)

Wang

et al. 2008

IEEE Electron Device Lett.

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We report the observation and utilization of boron segregation in trench MOSFETs (UMOS) to reduce on-resistance. A trenched LOCOS process has been applied to a UMOS structure to reduce the gate-to-source overlap capacitance (C gs ), and it is observed that not only 40% reduction in C gs is achieved but also 45% reduction in specific on-resistance (R on,sp ). Figure of merit is improved by 58%. TSUPREM-4 doping profile simulation at the silicon and oxide interface revealed the presence of boron segregation. On-resistance reduction is attributed by the shortened vertical channel length due to boron segregation. Index Terms-Boron segregation, figure of merit (FOM), on-resistance, trench MOSFETs (UMOS), trenched LOCOS process.

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“…2. The LOCOS UMOS achieved a breakdown voltage of 73 V and R on,sp = 85 mΩ · mm 2 at V gs = 3.5 V. The on-resistance reduced to R on,sp = 60 mΩ · mm 2 at V gs = 10 V [5].…”

Section: Resultsmentioning

confidence: 94%