A 700-V Device in High-Voltage Power ICs With Low On-State Resistance and Enhanced SOA

Yang, Fu-Jen; Gong, Jeng; Su, R.Y.; Huo, K.H.; Tsai, Chun-Lin; Cheng, Chuan; Liou, Ruey-Hsin; Tuan, H.C.; Chen, Huang-Chin

doi:10.1109/ted.2013.2273573

Cited by 28 publications

(6 citation statements)

References 12 publications

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“…However, the Ron increased significantly due to an extra current path underneath this region. Then, in order to improve the Ron resistance [16][17][18][19][20][21][22][23][24], this LOCOS extra current path should be reduced. Unfortunately, by reducing the extra current path, the drain peak field is too close to the gate edge and the breakdown voltage will be significantly reduced.…”

Section: Device Structurementioning

confidence: 99%

Optimized Design of the 100-V Silicon Based Power N-Channel LDMOS Transistor

Chen¹

2020

MCMS

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In power integrated circuits (PICs), it is desirable to minimize the area of a power device region while maximizing its performances (i.e., higher breakdown voltage and lower on-resistance). Therefore, the area of a power device region mainly determines the total chip size and hence the cost. An optimized design of breakdown voltage and on-resistance in a power n-channel lateral-diffused MOSFET (nLDMOS) was investigated in this paper. Two-dimensional process and device simulators, such as the TSUPREM4 and Sentaurus EDA tools, will be used to predict the device characteristic behaviors. Eventually, it can be shown that a 100 V device will have an optimized breakdown voltage about 156.7 volts and onresistance R on about 40.61 mΩ-cm2 under the V gs -V th = 5 V and LOCOS spacing d= 6 μm situations.

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Section: Device Structurementioning

confidence: 99%

Optimized Design of the 100-V Silicon Based Power N-Channel LDMOS Transistor

Chen¹

2020

MCMS

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“…2(b) is the distributions of vertical electric fields in the drift region with W T = 1 lm and t T = 7 lm for the BID MOSFET with a p-silicon and without a p-silicon, respectively. It can be seen that, for the device with a p-silicon, the p-silicon leads to lateral depletion of the drift region not only from the top side but also from the bottom side like a Double-RESURF [21], that's to say, the n-drift region is accelerated to full depletion before avalanche breakdown occurs. A more uniform vertical electric field is obtained and V L2 in Fig.…”

Section: Parameter Valuementioning

confidence: 99%

A low specific on-resistance power trench MOSFET with a buried-interface-drain

Chen

Jin

et al. 2015

Superlattices and Microstructures

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“…Laterally diffused metal oxide semiconductor (LDMOS) devices have been widely adopted in power integrated circuits due to its high Breakdown Voltage (BV) and low speci c on-resistance (R onsp ) [1][2][3][4][5]. It is the key determinant of the performance, cost, and integration level of power integrated circuits [6,7]. Currently, the conventional device design approach relies on simulation tools such as Sentaurus, Medici, Silvaco and so on.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

Xu,

Tang,

Zhu

et al. 2024

Preprint

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Shallow Trench Isolation laterally diffused metal oxide semiconductor (STI LDMOS) is a crucial device for power integrated circuits. In this article, a novel framework that integrates an optimal objective function, Bayesian Optimization (BO) algorithm and Deep Neural Network (DNN) model is proposed to fully realize automatic and optimal design of STI LDMOS devices. On the one hand, given the structure of device, the DNN model in the proposed method can provide the ultra-fast and high-accurate performance estimation including breakdown voltage (BV) and specific on-resistance (Ronsp). The experimental results demonstrate 98.68% prediction accuracy in average for both BV and Ronsp, higher than that of other machine learning (ML) algorithms. On the other hand, to target the specified value of BV and Ronsp, the proposed framework can fully automatically and optimally design the precise device structure that simultaneously achieves the target performance with the optimal figure-of-merit (FOM) of device. Compared to Technology Computer Aided Design (TCAD), there is only 0.002% error in FOM and 2.83% average error in BV and Ronsp. Moreover, the proposed framework is 4000 times more efficient than other conventional frameworks. Thus, this research provides experimental groundwork for constructing an automatic design framework for LDMOS device and opens up new opportunities for accelerating the development of LDMOS device in the future.

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A 700-V Device in High-Voltage Power ICs With Low On-State Resistance and Enhanced SOA

Cited by 28 publications

References 12 publications

Optimized Design of the 100-V Silicon Based Power N-Channel LDMOS Transistor

Optimized Design of the 100-V Silicon Based Power N-Channel LDMOS Transistor

A low specific on-resistance power trench MOSFET with a buried-interface-drain

An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

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