A 70 Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10 b ADC and FEC decoder

Abstract

A variable-rate IF-sampled QAM receiver integrated circuit operates at symbol rates from 1 to 7MBaud in 4, 16, 32, 64, 128, 256, and 1024-QAM. The QAMreceiveris amonolithicmixed-signal device implemented in a 0.5pm triple-level metal single-poly CMOS process. Thedeviceincorporates a lObA/Dconverter, analogPLLs, interpolating demodulator, square-root raised cosine receive filters, timingkarrierrecovery loops, 20-tap complex equalizer, and a ReedSolomon forward error correction (FECI decoder that is compliant with European digitalvideo broadcasting (DVB) and Digital AudioVisual Council (DAVIC) standards [l]. Applications of this QAM receiver include digital cable-TV set-top terminals, cable modems, and digital microwave radios.A top level functional block diagram of the QAM receiver including an RF front-end is illustrated in Figurel. The integrated 10b A/D converter of the QAM receiver accepts a 2 V differential input up to 32MHz sampling rate. The digitized 18, centered data stream from the MD converter is demodulated to baseband in-phase (I) and quadrature (Q) channels by downmixing with cos(~cd2) and sin (nd2) [a]. The A/D converter is clocked by a crystal referenced integrated PLL at a fixed rate incommensurate with the symbol rate of the receiver. The reconstruction and symbol timing recovery uses a polynomial interpolator 131 Given two successive input samples using a canonic signed d i p t (CSD) architecture [21 duced by the RF tuner. The phase discriminant is filtered by an integral-plus-proportional lgop filter where the output drives a quadrature direct digital frequency spthesizer (QDDFS) 141. e phase derotator loop The complex equalizer consists of two transpose-form adaptive FIR filters -an 8-tap feedforward (FFE) filter and a 12-tap decision feedback (DFE) filter. Each filter emplqys q parallel-tap architecture that allows simple cqntrol distribution and dqta , as well as convenient scalability for ifferent equalizer spans (Figure 2). TheThe fundamental computational core of performs one copplex multiply-qpcumulate operation plus one corppleg coefficient update per symbol period qaing a single multqlier and two adders tiThe FEC decoder consists of 4 blocks: frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) error correction, and derandomization. The frame synchronization block recovers MPEG framed data streams as defined in the DVB and DAVIC specification. The programmable convolutional deinterleaver is compatible with the Ramsey type I11 approach. The interleaving depth, 1,isprogrammablefrom 1=1-12,204whereIdivides204.An on-chip FL4Mis provided for I=1-12 andcontrol is suppliedfor an offchip RAM for 1~1 2 .The RS decoder processes the t = 8(n,k) = (204,188) shortened RS code, defined by the generator polynomial g(x) = (x+aO)(x+al) ... (x+a15) and the primitive polynomial p(x) = x8+x4+x3+x2+1. Derandomization ofthe data streamis performed to undo the energy dispersal function inserted a t the encoder and is based on the generator l +~l~+ x~~.The QAM receiver is extensively tested...

A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

“…This corresponds to a maximum bit rate of 64.44 Mbits/s for 256-QAM signals. [31] n/a 4 → 64 5 MBaud SAG-DD Shen [27] 0.25 µm 4 → 256 10 MBaud CMA, DD Tan [28] 0.5 µm 4 → 256, 1024 7 MBaud S-LMS D'Luna [29] 0.35 µm 4 → 256 7 MBaud S-LMS Wu [30] 0. 6 The functionality and timing of the final design was verified at the gate-level using the output gate-level netlist and standard delay format files produced by Quartus II for NC-VHDL.…”

“…A number of recent application-specific integrated circuits (ASIC) QAM demodulator designs have been implemented that incorporate blind [24][25][26][27] or trained adaptive equalizers [28][29][30], which are listed in Table 3. The symbol frequency of these implementations range from 5 to 10 MBaud, while the signal constellation ranges from 4-QAM to 1024-QAM.…”

A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder

“…For typical DVB-C applications with 6.875 MBaud, our demodulator can compensate frequency offset more than 1MHz, which is much wider than those in [2][3][4][5][6][7][8]. In digital TV applications, there is no training signal; therefore the receiver should demodulate the signal blindly.…”

“…The frequency detector receives soft decision of equalizer and estimate the frequency offset. Once the frequency offset is eliminated, the carrier recovery loop switches to phase detecting mode, which use normal decision directed algorithm [2,10]. If decision directed phase detecting algorithm is used without frequency detector, the carrier loop is sensitive to the channel impairments, which makes demodulation unstable.…”

“…[2][3][4][5][6][7][8] have proposed several chip implementations of QAM demodulators. [2] presents a QAM receiver integrated with 10-bit ADC (Analog to Digital Converter) and FEC (Feed-forward Error Coding) decoder, but it has several shortages, such as lacks the capability to direct sample the signal with 36M/44M IF, fixed sampling rate with 4x IF frequency, low carrier frequency offset acquisition range. [3] introduces a QAM demodulator with carrier frequency offset range of 80KHz, which has relative large area and less integration level.…”