A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder

Tan, Loke Kun; Putnam, J.; Lü, Fang; D'Luna, L.J.; Mueller, D.; Kindsfater, K.; Cameron, K.; Joshi, R.B.; Hawley, R.; Samueli, H.

doi:10.1109/4.735705

Cited by 25 publications

(1 citation statement)

References 7 publications

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“…A third set of work is done by Samueli et al [17,35,20]. In these papers, Sammueli et al studied algebraic transformation and relaxed lookahead pipelining techniques that enable power-supply voltage to be reduced, while maintaining the same throughput.…”

Section: Previous Work On Low Power Adaptive Decision Feedback Equalimentioning

confidence: 99%

Design of a power-scalable digital least-means-square adaptive filter

Ng¹,

Chandrakasan²

Proceedings of the Sixth International Symposium on Signal Processing and Its Applications (Cat.No.01EX467)

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This thesis describes the design of power-scalable digital adaptive equalizer for pulse or quadrature amplitude modulation communication systems, using synthesis and place-and-route tools. DSP based modem applications such as gigabit Ethernet transceivers require channel equalization. Because of the high rate and computation complexity involved, adaptive equalization filters consume a lot of power. Currently, equalization is typically hardwired instead of using a digital signal processor. Yet, there is a need for the equalization filters to be scalable to different channel and bit rate requirements. Synthesis and place-and-route tools enables the designer to focus on higher-level aspects of the design instead of at the transistor level. In this thesis, we have used adaptive tap length and precision techniques to design a digital adaptive equalizer whose power consumption is scalable to the precision requirements.

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Section: Previous Work On Low Power Adaptive Decision Feedback Equalimentioning

confidence: 99%