Design of a power-scalable digital least-means-square adaptive filter

Abstract

This thesis describes the design of power-scalable digital adaptive equalizer for pulse or quadrature amplitude modulation communication systems, using synthesis and place-and-route tools. DSP based modem applications such as gigabit Ethernet transceivers require channel equalization. Because of the high rate and computation complexity involved, adaptive equalization filters consume a lot of power. Currently, equalization is typically hardwired instead of using a digital signal processor. Yet, there is a need for the equalization filters to be scalable to different channel and bit rate requirements. Synthesis and place-and-route tools enables the designer to focus on higher-level aspects of the design instead of at the transistor level. In this thesis, we have used adaptive tap length and precision techniques to design a digital adaptive equalizer whose power consumption is scalable to the precision requirements.