A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology

Wu, Liang; Weizel, Maxim; Scheytt, J. Christoph

doi:10.1109/icecs46596.2019.8965046

Cited by 6 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…With the advanced technology and an adapted architecture, the power consumption of the analog core could be reduced by a third, and its active area by a half. The circuit in [5] with a comparable SiGe technology uses the SEF as well, but no preamplifier, resulting in a slightly higher bandwidth, but lower sampling rate, input voltage swing and linear frequency range with a comparable DC power dissipation in the analog core. For sampling front ends above 40 GS/s, the presented track-and-hold circuit exhibits the highest bandwidth.…”

Section: Resultsmentioning

confidence: 99%

64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology

Thomas

Berroth

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Time-interleaving of energy-efficient data converter cores enables record symbol rates in electronic receivers. High-speed applications like optical data transmission or direct down-conversion in wireless mmWave receivers require ultra-high bandwidths and symbol rates, which CMOS data converters and especially their analog front ends cannot provide to date. We demonstrate a 64-GS/s track-and-hold circuit with a large-signal bandwidth of more than 61 GHz without any area-consuming peaking inductors, designed and manufactured in a 90-nm SiGe BiCMOS technology. The analog sampling front end exhibits a third harmonic distortion of -45 dBc to -32 dBc within the available frequency range of 50 GHz, which is better than the 5-bit requirement for 1.0-Vpp input signals. The ultra-high bandwidth of the circuit is twice as high as reported for CMOS data converters and in the range of broadband germanium photodiodes. This improves the bottleneck in hybrid integrated optoelectronic receiver front ends significantly. It is suited for time-interleaving of two channels with a doubled symbol rate of 128 GBaud, and the linearity allows to use it with 6-8-bit data converters.

show abstract

Section: Resultsmentioning

confidence: 99%

64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology

Thomas

Berroth

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…Although the ADCs and DACs using SiGe and InP processes realized higher sampling rate and wider BW [5,6,7,8], they are not compatible with CMOS-based DSPs. In response to these challenges, previous studies have recently started developing analog multiplexers (AMUXs) [1,9,10,11,12,13,14,15,16] and analog demultiplexers (ADEMUXs) [17,18,19,20,21,22,23,24,25], which simultaneously achieved high data rate and compatibility between ADCs/DACs and DSPs. In this paper, a 2:1 AMUX in IHP's 130-nm SiGe BiCMOS process is introuduced.…”

Section: Introductionmentioning

confidence: 99%

A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process

Fan,

Wang,

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a 2:1 analog multiplexer (AMUX) using IHP's 130-nm SiGe BiCMOS process. The proposed AMUX expands the analog bandwidth (BW) of CMOS-based DACs by introducing interleaving sampling technique, thus improving the data rate of single lane in modern optical communication systems. Meanwhile, a detailed analysis of process selection which particularly focuses on material and device considerations is adopted, and a principle of the BW expansion is comprehensively discussed. The AMUX exhibits a BW > 70 GHz, achieving a data rate of 200 Gb/s under PAM-4 modulation.

show abstract

Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock

Thomas

Berroth

2021

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

View full text Add to dashboard Cite

A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology

Cited by 6 publications

References 3 publications

64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology

64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology

A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process

Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock

Contact Info

Product

Resources

About