A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection

Philpott, R.A.; Kertis, R.A.; Richetta, R.A.; Schmerbeck, Timothy J.; Schulte, D.

doi:10.1109/4.278338

Cited by 24 publications

(2 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Class IV partial response equalization followed by a maximum likelihood detector (PR4ML) has successfully replaced peak detectors in many current hard disk drive products [4], [5], [17]. In a linear channel dominated by additive white Gaussian noise, PR4ML clearly outperforms peak detection.…”

Section: Introductionmentioning

confidence: 99%

A parallel architecture for multilevel decision feedback equalization

Kenney

Melas

1998

IEEE Trans. Magn.

View full text Add to dashboard Cite

The data rate in a decision-feedback detector is limited by the critical timing loop. Within one clock cycle, the result of a decision by the comparator must be able to make its way back through the feedback filter and summing junction to reappear at the comparator input. It is shown here that multilevel decision feedback equalization (MDFE) can be readily modified to allow two clock cycles for the completion of this critical timing loop. This is accomplished by readjusting the forward equalizer until the first coefficient in the feedback filter is forced to zero. There is no significant degradation in performance in the application as a read/write channel for a hard disk drive. A parallel architecture can then be developed in which the entire structure is clocked at one half of the channel clock rate. A mixed analog/digital circuit topology is suggested for implementing this structure. A further proposal is that the feedback filter can be implemented as a set of small lookup tables, each pipelined to achieve highest data rate.

show abstract

Section: Introductionmentioning

confidence: 99%

A parallel architecture for multilevel decision feedback equalization

Kenney

Melas

1998

IEEE Trans. Magn.

View full text Add to dashboard Cite

show abstract

“…Previously-published PRML channels include a 56MWs channel design but without an on-chip programmable filter, synthesizer or servo demodulator [2]. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using arate-fY9 code.…”

mentioning

confidence: 99%

An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Choi

Pierson

Trafton

et al.

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

View full text Add to dashboard Cite

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD) [l]. Previously-published PRML channels include a 56MWs channel design but without an on-chip programmable filter, synthesizer or servo demodulator [2]. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using arate-fY9 code. Figure 1 shows the HDD system containing this analog front-end signal processor and its companion digital ASIC. The digital ASIC contains the FIR filter and Viterbi detector. Multi-zoned disk-drive operation is supported by this chip. Sophisticated control of chip functions is provided, including a versatile power-management scheme allowing the chip to cycle through different operating modes. Operating modes include idle, servo, read, and write. A block diagram of the IC is shown in Figure 2.The AGC has exponential gain-versus-control-voltage transfer function for consistent attack and decay time-constants regardless of input signal size. AGC input impedance switches to a low value during write mode for quick recovery from dc transients. There is an internal offset-correction loop around the AGC so that ac coupling capacitors between the AGC and filter are not required. There is also a digital mode that allows fine-tuningof the AGC gain to optimize the PRML detection in the digital ASIC.The programmable 7th-order equiripple continuous-time filter uses a Gm-C architecture for high frequency performance. A unique range switching and tuning technique is used: 32 frequencyranges covering the frequency span from 6 to 33MHz are selected by a combinational switching of a 3b Gm array and a 2b capacitor array. Frequency programming is accomplished using two switching arrays to avoid either large Gm or large Cap spread. Frequency tuning to compensate for process and temperature variations is provided by a phase comparison circuit(Figure3). EachGmstageintheslavefilteriscalibrated by a master phase-locked loop (PLL) that includes a duplicate filter biquad stage to determine the lock point. This tuning system creates a calibrated gate voltage that seta the Gm of all Gm-C stages, with the Gm and C variations calibrated out by locking to an external accurate frequency reference that is also required for ADC and PLLoperation. This filter also serves the dual role of data and servo filters. Boost equalization is performed by the FIR filter in the digital ASIC.The ADC is a differential input 6b flash converter capable of running at 72MHz (Figure 4). This ADC accepts the amplified and filtered analog read signal and produces a digital word representing the signal voltage at the point of each sample. The ADC is clocked by the internally generated code-rate clock, or by anexternalreferenceclock. The ADC, with the synchronizer PLL, creates a synchronous data conversion system that allows fewer data conversions to be used to derive the digital data from the analog waveform off the disk. The ADC synchronously sampl...

show abstract

Practical Design and Applications of Current-mode Systems

Mohan¹

2003

Current-Mode VLSI Analog Filters

View full text Add to dashboard Cite

A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection

Cited by 24 publications

References 13 publications

A parallel architecture for multilevel decision feedback equalization

A parallel architecture for multilevel decision feedback equalization

An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Practical Design and Applications of Current-mode Systems

Contact Info

Product

Resources

About