Abstract:Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD) [l]. Previously-published PRML channels include a 56MWs channel design but without an on-chip programmable filter, synthesizer or servo demodulator [2]. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using arate-fY9 code. Figure 1 shows the HDD system containing this analog front-end signal processor and i… Show more
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