A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL

Park, Dongjun; Kim, Jongsun

doi:10.1007/s00034-019-01230-x

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…After the coarse TDC search operation, the fine DLL TDC search operation is enabled for the next two clock cycles. The fine DLL TDC adopts a Vernier delay line structure to achieve higher delay resolution [6,7]. Fig.…”

Section: B Locking Processmentioning

confidence: 99%

“…As the I/O bandwidth required for mobile devices, display devices, and computing systems increases, the operating speed of various I/O links is continuously increasing. To solve the clock skew related problems in high-speed I/O links and on-chip clock distribution networks, the use of a delay-locked loop (DLL) [1][2][3][4][5][6][7] is a must. Also, almost all high-speed DLLs need to incorporate a duty-cycle corrector (DCC) to adjust the duty-cycle of the DLL output clock to 50%.…”

Section: Introductionmentioning

confidence: 99%

“…One of the most important things in designing a lowpower system-on-chip (SoC) or a memory device is the capability of fast power mode switching. It has been reported that the DRAM's power consumption can be reduced dramatically if the DLL lock time can be reduced to around 10 ns [7,8]. Also, there have been attempts to improve the lock time of either DLL or DCC by using timeto-digital converters (TDCs).…”

Section: Introductionmentioning

confidence: 99%

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A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC

Kim

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A new time-to-digital converter (TDC)-based fast-lock all-digital delay-locked loop (DLL) with a built-in duty-cycle corrector (DCC) is presented. The proposed DLL utilizes a new shared TDC-based phase correction and dutycycle correction scheme that results in a fast lock time of less than 22 clock cycles. Conventional DCC embedded DLLs usually have a limited operation frequency and slow lock time. However, in the proposed new architecture, since the DCC is built into the delay line of the DLL, it can operate at high speed of up to 3.5 GHz. Implemented in a 65-nm 1.0V CMOS process, the proposed DLL achieves a frequency range of 0.8-3.5 GHz, and the duty-cycle correction range is ±20% at 0.8 GHz. It achieves an effective p-p output clock jitter of 5.4 ps at 3.5 GHz, occupies an active area of 0.08 mm 2 , and the power consumption is 8.0 mW at 3.5 GHz.

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Section: B Locking Processmentioning

confidence: 99%